Well, there are probably multiple ways of doing it, but the first thing that comes to mind for me is using the Data_Available signal. If you are using the FIFO CLIP then there should be a line called "Data_Available" which is true when the following conditions are BOTH TRUE:
A) There is data in the FIFO
B) The internal circuitry of the device is ready for you to read the next FIFO element.
So, what I would do is:
1) Stop putting data into the FIFO
2) Start checking the Data_Available line, and while it is true, do a read from DRAM, but throw away the data.
3) I believe that the DRAM is at a speed such that if you are running your DRAM loops (in LabVIEW FPGA) at 40MHz, then condition B above should never be an issue. That would mean that as soon as Data_Available goes false, your buffer should be clear.
HOWEVER.... I think the safest way to ensure that the FIFO is done clearing is to check Data_Available on a few consecutive cycles of your Single Cycle Timed Loop and make sure that they are all falses. If you see Data_Available=false on 3 or 4 iterations of the 40MHz clock in a row, then I think you can be pretty certain the buffer is clear.
Hope that helps.
