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High Throughput Phase lock loop (PLL) in FPGA

I might not be asking the right question, so bare with me.  I'm digitizing a ~450kHz square wave at 80MHz (so ~176 AI points per square wave period).  The square wave's frequency may slowly drift (a few % over minutes).  I would like to know the phase of the square wave at every AI sample.  This sounds like a job for a Phase lock loop. 

 

I'm struggling with how to implement this.  The FM demodulator example and niFPGARFv2 PLL.vi implementation look like they need to pass the acquisiton data from a slower loop (data acquistion loop) to a faster loop (analysis) since the PLL routine doesn't have high throughput (needs many cycles to output a valid result).  Is my understanding correct?

 

Can I put the PLL analysis in the same loop as my acquisition and discard AI samples when the PLL analysis is busy?  (I think the VCO would need to run with a throughput of 1 sample per clock? Is this true?)

 

Or can the PLL throughput be increased at the cost of some precision? (I would be very happy with 10-bit precision).

 

 

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D*,

 

Can you post the VIs which you're referring to, and give us some more detail about your overall application?

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My application is using a NI 5734 flex rio digitizer. The digitizer is simulateously sampling 4 channels and the digitizer ADC clock is set by a specific 80MHz external source.  One of the 4 digitized channels is a going to be a ~450kHz square wave. At 80MHz digitization, the square wave will have a period of ~176 samples.  The FPGA needs to process each data point from the other 3 data channels based upon the phase of the ~450kHz square wave when each sample was digitized.  Therefore the phase of the square wave is needed for every ADC clock tick (i.e. at 80MHz). 

 

 

My initial solution was to measure the period of the square wave by counting the ticks between rising edges and compute phase based upon that, but it's not accurate enough (this has an error of up to 2/176 about 6-bits of precision).

 

 

I'm looking for a PLL that can lock to the 450kHz square wave that is being digitized at 80MHz.  The PLL analysis needs to be able to output a phase value (between 0 and 1, with say 10-bits of precision) for each ADC sample (i.e. at 80MHz).

 

 

I was looking at this example :

 

https://decibel.ni.com/content/thread/3562

 

Where there is a DMA FIFO that passes every data point through the PLL analysis.

 

 

 

And the FM demodulator example here :

 

https://decibel.ni.com/content/docs/DOC-1331

 

Where there is a target scoped FIFO that passes every data point through the PLL.

 

 

 

So in both of these examples the PLL analysis is run asynchronously to the data acquisition, and consumes every data point.  I think (correct me if I'm wrong) this is generally because the PLL analysis throughput is not 1 data point per cycle?  Since I won't be able to run the PLL analysis loop many times faster than 80MHz, I don't think this is an option for me.  Do I need to downsample the acquisiton?  Or is it okay if the PLL analysis misses data points (I would guess this would be okay if the VCO increments on every clock?)?

 

 

 

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