5641R External Clock

[kadede]

Recently we have met with an issue when using external sampling clock on 5641R. When we use  5641R Internal,everything is O.K. Signal we get is stable. But when we use External Clock (The “Clock In “ is connected to the Sine signal generated by Pxie5652,10dBm). Abnormal phenomena: The amplitude is not stable within the acquisition time. Settings: Ni 5640R configure Timebase.vi: CDC Clock Source=SMB External Ni 5640R ADC Configue NCO.vi: Previously Configured Clock Frequency= Sine signal generated by Pxie5652.

Would you please tell me how to solve it?

[JVP]

Hello,

I would like to ask you a few questions and suggestions about your setup.

1) You have mentioned that you are using NI 5640R Configure Timebase.VI, Using this the clock that you bring in can only be used to PLL (Reference Clock). In order to use the CLK IN as an external sample clock, you will have to program in LabVIEW FPGA, based on the help documentation below:

2) If you are programming in LabVIEW FPGA, would you mind uploading your code, so I can take a look at it?

3) What is the clock frequency, you are importing?

Best Regards,

Jignesh P

Applications Engineer

[JVP]

Hello,

After looking into this a little more, I realized that you are using LabVIEW FPGA to program. I would still like to know, what is the frequency for the CLK IN? Also, could you upload your code, so that I may take a look at it?

Best Regards,

Jignesh P

Applications Engineer

[Heeyoon.L]

Hi. I'm using 5772R. I generated clock signal (100~150MHz) and would like to use it for external clock (CLK_IN). First questions is: can CLK_IN signal be just a sinusoidal signal or should it be TTL signal? Second question is: can speed of CLK_IN signal be slower than 400MHz? ( datasheet says the range of CLK_IN is 400MHz-800MHz, so I wonder if the signal can be below 400MHz) In the labview, I'm using the base code, 'Clock Select.ljproj', 'Clock Select (FPGA).vi' is compiled first, and then 'Clock Select (Host).vi' is run. I set the clock source as 'External Clock (CLK_IN)', and clicked 'Go', however, the signal shown on the plot doesn't seem to be externally clocked data.. The data seems to be clocked based on the internal clock (400MHz). How can I use CLK_IN signal for sampling the AI0 signal? Should I write a FPGA code in different ways? Thanks, Heeyoon