PXI-5122 external clock rate

[JoeSavage]

Hello, I am curious as to why an external sample clock is limited to the range of 30MHz - 105MHz for the PXI-5122.     I would like to synchronize to an external 3.84MHz or 1.28MHz clock.    The only solution I can think of is to use an external PLL circuit to produce a multiple of the external 1.28/3.84MHz clock, but that's not a very convenient solution.

Thanks,

Joe

[Matt_E.]

Hi Joe,

The 30 MHz limit is set by the minimum conversion rate of the ADC on this board.  Generally speaking the ADCs with a higher speed maximum conversion rate will also have a higher minimum conversion rate, so if you are only wanting to clock in the <4MHz range you should look for a slower board.  We do have some boards that support a lower conversion rate than the 5122 but I am not sure if they meet other requirements you have.  The USB-5132 & USB-5133 have a minimum rate of 1MHz but the clock input on these boards only accepts 3.3V CMOS input levels.  The PXI-5105 will accept down to a 4MHz clock and has a more general purpose AC coupled input.

If your source is able to generate frequencies from 1MHz to 20MHz in 1MHz increments, can also accept this as a reference clock input which it can then use to lock its internal clock to.  The only other option aside from the one you mentioned in your email is you could export the 5122's internal sample clock and lock your source to it if your source has that ability.  

Since your high speed digitizer line focuses primarily on signals > 10MHz you may also want to look into our simultaneous sampling data acquisition products (DAQ)  A board like the PXIe-6126 for example might be a good fit.  It is aimed at sampling rates below 4MS/s and supports external clocking.  PXIe-6124  There are other boards in this category as well so look around for the one that best matches your needs.

Hope this helps,

-Matt

[JoeSavage]

Hi Matt, thanks for your reply.  The confusing thing is that the 5122 supports a sampling rate as low as 1.5kS/s using the internal clock, but not using the external clock.  

I actually am already using a PXI-6124 to acquire data using the external 1.28MHz clock, but I can't use it for the 3.84MHz clock because I need to sample two channels, and the 6124 has a 2.5MS/s limit for multiple channels.   We require at least 14 bit resolution, so the 6115 is not feasible.

One other solution that I am considering is oversampling the waveform at, say, 100MS/s, then using fractional resampling/interpolation to downsample to the desired rate.

Regards,

Joe

[Matt_E.]

The 1.5kS/s using the internal timebase is using decimation so the actual sampling rate of the ADC is still 100MHz but we are throwing out some of the samples.  You can do this with external sampling as well but you still have to enforce the minimum sampling rate.

-Matt