Looking for an example of continuous data collection with a NI5771/PXIe7966R combination. While the getting started example is a great start it is designed for a data snapshot not streaming. Initially I want to stream raw waveform data to the screen but eventually will need to compute spectrum for indivdual 512 point segments of the data stream. Anything like this out there?
Currently, there are no existing examples which demonstrate streaming functionality as you've mentioned.
Since the device front-end (5771) will acquire more data than you can move across the PXIe Gen 1 x4 bus (on the 7966R) you would need to modify your current code to decimate the samples, and only return every Nth sample to the host.
For example, if sampling at 1.5GS/s with this 8-bit digitizer, you are acquiring 1.5GB/s of data. If you decimate by two (N = 2), you will be able to stream (1.5GB/s / 2 😃 750MB/s. This streaming rate should be obtainable for long-term acquisitions. If you have any other bottlenecks in your system (slower controller, hard disk drives) then you may need to decimate further (N = 3 or N = 4).
Sorry, my request was poorly worded.
You are absolutely correct that I will not be able to continuously stream data to the host with the current PXIe bus throughput limit. However, in my particular application I will collect data for no more than 100 microseconds and will have up to 150 microseconds before my next collection period begins (can be viewed as a duty cycle of 40%). During the 150 microseconds of collection "down time" I will need to perform multiple 1024 point FFT's and transfer the resulting frequency data to the host computer.
Just wondered if there was an example like this floating around that would serve as a bit closer jumping off point for my development.
Really looking for an example of how to programatically trigger the 5771 to collect a 100 uS burst of data at a user specified interval (4 kHz). The example uses either a software trigger (in the form of user button press) or a data trigger (analog voltage crossing). Given the interval I imagine that I will need a clock based trigger but am unsure how to proceed. Thoughts anyone?
Currently, the only 5771 examples that I am aware of are the three examples are installed with the FlexRIO Adapter Module Support. All three of these examples impliment a software trigger from the host/user. Slight changes could be made to the Getting Started Example to send that software trigger at 4kHz intervals from the Host. Or, you could take that trigger from the host as a "start" signal for a counter on the FPGA that counts to one period of a 4kHz pulse. The 100uS burst of data is another simple modification of the code as the code allready takes a 'x' number of samples as defined by the host. Some quick math will tell you the number of samples needed to fufill a 100uS burst, or you could just have LabVIEW calculate that value based on a given burst width. The biggest concern of this is if the data handling mechanisms can handle a burst of 100uS. You may have increase the depth of the DMA FIFO on the FPGA side or add some sort of data buffer (such as a Target Scoped FIFO, Memory, or DRAM) between the IO Nodes and the DMA FIFO to handle the bursty data. The "TIS" example for the 5771 shows an example of a Target Scoped FIFO Data buffer between the IO Nodes and the DMA FIFO.
Very interesting discussion.
I have some tasks to find pulses in IF path of my RF device. I need to analyse about 100 MHz bandwidth for pulse serach. When I found it (pulse) I need to know pulse frequency and make some pulse on external DIO pin.
As I understand, I should take FlexRIO card with some digitizer adapter, for exaple N5791 and then continiuosly do real-time FFT with some king of data FIFO structure, where I will put new samples from digitizer module and delete old.
Question: what is the maximum sample rate for Real-Time FFT for 7966R FlexRIO card ?
Do you have some information about pulse search with FlexRIO cards ? (Maybe some examples, test results e t.c.).
Through put is going to be dependant on a couple of things. Mainly clock rates and fpga size. The device you listed has a Xilinx Virtex-5 SX95T. We have a dev zone that talks about benchmarks that we have done on some of the Virtex 5 chips. This paper discusses FFT and other considerations.
LabVIEW FPGA has both DMA FIFOs to communicate data with the Real Time target and it has Target Scoped FIFOs for use within the FPGA itself. Lastly you can also look through the documentation for the Virtex 5 family to find further information about benchmarks that you might need.
There is an example that shows how to use the FFT function in LabVIEW inside a SCTL if your data rate is slower than the loop rate. The example is called FFT with Handshaking - R Series. You can find it by going Help >> Find Examples. Once there navigate to Toolkits and Modules >> FPGA >> FPGA Fundamentlas >> Analysis and Control.
This is a very interesting question you present, however I'm having difficulty seeing how it relates to the original topic.
Would you please create a new thread for this topic, and I'll be more than happy to work with you on it. Can you also link the new thread here so others in the future can find it easily.
Furthermore can you elaborate on what you mean by "About 100 MHz"? As the 5771 has a 900 MHz bandwidth. Are you limted by the resolution of your acquisition? What about the resolution of the frequency of interst, how accurate does that need to be?
I'll be looking for your new post. Thanks!