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NI 5761 IO Module Clock 0 Compiled for 100MHz in Single/Multiple Sample CLIP Example Projects

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Hi,

 

I was trying to wrap my head around the NI 5761 Multi Sample CLIP (v4.1.0) because the CLIP provides 250 MSPS data but the IO module requires a 200 MHz clock.  I'm thinking, "NI must handle the clock conversion, fine, but I hope the diagram runs at 125 MHz...otherwise I'm really confused"  So I look at the IO Module Clock 0 configuration in <labview>\examples\FlexRIO\IO Modules\NI 5761\NI 5761 Getting Started\NI 5761 - Getting Started.lvproj and to my surprise it's compiled for 100 MHz.

 

I checked the 7965 target in NI 5761 Single Sample CLIP\NI 5761 - Single Sample CLIP.lvproj and IO Module Clock 0 was compiled for 100 MHz there as well.

 

I don't understand the difference between the data rate and the 200 MHz IO module clock selection, and it would be nice to understand this but not necessary.  I also don't understand the difference between the data rate and the IO Module Clock 0 configuration that drives the SCTL containing the IO Node.  I do need to understand this in order to move forward.

 

Thanks for any help,

 

Steve K

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Version 4.1 of the Multisampkle CLIP doesnt use IOModClock0. It uses the CLIP Clock that comes directly from the CLIP. In this case, that clock is named 'Data Clock'.

5761_clip_clock.PNG

 

If you look at the LabVIEW Help entry for the 5761 Multisample CLIP it mentions that the Data Clock runs at half the rate of the clock that the ADC uses as a sample clock.

 

5761_clock.PNG

 

If you look at the spec sheet for the 5761 you'll see that the internal osciallator runs at 250MHz. This would give you a Data Clock of 125MHz if you are using the internal osciallator to sample data.

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Thanks David, so...what's this 200 MHz clock for:

 

Untitled1.png

 

 

 

More importantly, I still need to understand IO Module Clock 0 driving the SCTL in the example program.  I'd think the 100 MHz SCTL would decimate the ADC:

 

Untitled2.png

 

-Steve K

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Solution
Accepted by topic author Pie566942.0

The CLK200 in the Clock Selections is used to drive portions of the fixed logic that are internal to the CLIP. Certain FlexRIO CLIPs may only require a CLK40, this one requires both a CLK40 and a CLK200 to correctly run its fixed logic. So it looks like everything is ok with regards to that. 

 

Unfortunately the example incorrectly uses IOModClock0. The SCTL that the AI IO node resides in should use a clock resource that says 'Data Clock'. We've updated the examples in more recent versions of the driver, but you appear to be using a version of the driver where a CLIP that uses the Data Clock is the most recent CLIP available for the 5761, but the example has not yet been udpated to use it.

 

5761_SCTL.PNG

 

 

 

 

 

 

 

 

 

 

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Thanks David.  Good answer to my first question, and I'm not going crazy with my second question.

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Hi,

I am also stuck while executing the NI 5761 - Clock Select.lvproj example.I am new to labview fpga and am using PXIe 1075 chassis which has NI5761 adapter module and flexrio PXIe 7965R.There is an external clock fed through the arbitrary waveform generator and it is generating a chirp signal of 2-18 GHz which I wanted to sample through this example.But I am getting the same FlexRIO Error -61046.I am using Labview version 2012 sp 1.Any help would be appreciated as I am stuck trying to run this example from quite long.

 

Thanks

Aishwarya

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Hi,

I am also stuck while executing the NI 5761 - Clock Select.lvproj example.I am new to labview fpga and am using PXIe 1075 chassis which has NI5761 adapter module and flexrio PXIe 7965R.There is an external clock fed through the arbitrary waveform generator and it is generating a chirp signal of 2-18 GHz which I wanted to sample through this example.But I am getting the same FlexRIO Error -61046.I am using Labview version 2012 sp 1.Any help would be appreciated as I am stuck trying to run this example from quite long.

 

Thanks

Aishwarya

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The thread you are replying to is just about two years old so I would suggest making a new thread to address your problem specifically. I would also check to see if you get the same error when you select the internal clock options or if you only see this error when trying to use one of the external clocks. It would also help to know which function is throwing this error.

Matt J | National Instruments | CLA
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