FlexRIO Sampling Rate control

[Happyfrank]

I have a setup that will include a pair of PXIe-5774 FlexRIO digitizers.  I am new to LabVIEW FPGA so started with the example project 'Getting Started...'.  The main read SCTL is run from the 200MHz data clock.  It takes that last 16 samples from each channel and saves it to a DRAM FIFO.  I am looking to reduce the sample rate, but maintain equal spacing and allow this to be easily adjusted by the user.  I originally thought of using a decimation routine or averaging, but neither is working due to the requirement that the array size be known or would require other things that are not allowed.  I looked at the Rational Resample, but it did not appear that it could be programmatically controlled and it did not appear to work at a high enough frequency.

I am now wondering, if I reduce the clock rate for the main data read loop will that reduce the rate that the device samples or will it only reduce the rate that I pull data off the circular buffer.  If I cut the data rate in half will I completely miss the first set of 16 samples or will the device just sample at half the rate and I will essentially get every other data compared to reading at the full rate?  I am hoping to get something that does the latter.

I will likely need to be doing a similar thing with a PXIe-5745 Waveform Generator to reduce the frequency of the output.

[Happyfrank]

I have not yet been able to verify how my code functions, but I decided that due to the deterministic nature of the FPGA that I would have to hard code a single decimation routine for a particular frequency, rather than having the user select the frequency.

[NI代理商]

Hi, could you please tell me how's the issue going on? I met the same problem. Don't know how to change the sample rate on 5774

[HSD]

Hardcoding a decimation factor is the simplest solution.  The alternative (more complicated) is to add logic to select which samples to store (using the data valid) then pass that data to a set of logic that packs (there is a block in the Common IDLs that can do the packing part) the data to the same width that the DRAM expects.

One tip to simplify the selection logic is to only allow powers of 2 decimation or even easier is one or zero samples per cycle.  So if the I/O is providing 16 samples at a time you could allow for 1,16, 32, 64, ... decimation factors