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Re: sbRIO-9651: Need help with FPGA data write to DMA FIFO and sync it with RT DMA FIFO data read

Yes, from time to time, I miss some data values from the trigger point, and the missing data size is random (that's why I meant in the middle of stream). Similar to FPGA generate known data like you suggested, I do know how many data values are missing in a stream.

 

I do have an FPGA DMA FIFO time out, but I am not allowed to stop the 2.5ms periodic trigger nor slow down the data rate putting into DMA FIFO which is 10MHz.  However, the data size putting into the DMA FIFO can be adjusted since I am only interested in the first 1024 elements or a little more. 

 

I guess the problem might be that once a while the RT is out of sync or reading some stale data due to FPGA FIFO time out...

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