Use FPGA I/O peripherials on sbRIO-9651

[Kevin_Hooper]

Can I use the built-in FPGA I/O peripherals (I2C, SPI, etc) on the sbRIO-9651?

I know from the following from Xilinx Zynq reference manual:

1. There are I/O peripherals which can be used by the FPGA ARM processor.

2. The interfaces of each peripheral has configurable routing.

I find any LabVIEW Real-Time functions to use these peripherials (like the myRIO SPI VIs).

The FPGA sbRIO CLIP generator only seems to give options for UART, CAN and Ethernet pin usage.

[MrJackHamilton]

Kevin,

I am doing I2S on a current SOM project and have used working code from cRIO to do the job. I am not using an existing IP or 'drop' xilinx IP. It was done low-level in the FPGA.

My approach as been to do it low-level bit-bang style, as drop-in's are likely to come in future releases of the SOM software.

Basically, you can search for FlexRIO and cRIO examples and use that code in your SOM FPGA. Of course you have the additional task of creating the CLIP.

Luckily, we have the CLIP for the devkit, which incorporates numerous standard interfaces, so we have a guideline on how to configure the descrete I/O line configuration. When in doubt, configure the line TTL, di-directional.

Please post your good and bad experiences...I am also happy to share code where I can.

Regards

Jack Hamilton

[tannerite]

Kevin,

Currently, only the peripherals exposed in the sbRIO CLIP Generator are what you natively have. As Jack stated, you can incorporate IP from the Tools Network and other examples for I2C and SPI. The myRIO uses a LabVIEW FPGA core to handle the SPI and I2C communication.

If you require or believe it would be nice to have native Linux interfaces to peripherals like I2C and SPI, please let marketing know!

There is a feedback thread that our marketing team is using to collect feature requests and improvements, below. Make sure to include use cases and reasoning behind the requests so they can use that in feature planning.

https://decibel.ni.com/content/message/96720#96720

- Tanner

[MOONANI]

Kevin,

I also try to find a I2C module for NI 9651. I found a I2C driver in NI driver network, Install via VIPM .

I think that driver is desgined for conventioanl C-rio product.

When I try to link FPGA IO resource, I found som problem at bi-direction IO properties.

I'm not sure why clip generate three dirrefent IO type : xx_in, xx_out, xx_en

I think NI try to handle signal routing problem in advance at stage of LabVIEW program code. XX_en is used like a semaphore to protect mutual exclsution.

Anyway, I'm still find a new way to implement I2C driver in FPGA level. I think I should modified conventioal I2C enegine VI to adopt NI 9651

If I finish the job, I'll post again.

[jruhland]

What was the exact problem you're having?

I'm working on implementing the same thing on the SOM right now and according to the documentation (which I found at C:\Program Files (x86)\National Instruments\LabVIEW 2015\user.lib\_NI I2C IP\documentation) the output nodes (xx_out) are supposed to be permanently wired low. The I2C engine's outputs are actually inverted and wired to the output enable (xx_en) nodes and the engine toggles the output by switching them between low output and high impedance modes. As long as there are pull-up resistors attached to the I2C bus they'll get pulled high.

I'm not sure what to do about the "Output Enable Done" nodes because the clip generator doesn't provide those for any of the FPGA IO resources on the sbRIO-9651. I'm going to try wiring them straight to a boolean constant and see if it works.