Unroutable Placement Error After Migration To Labview 2016

[danielsu]

Hello Everybody,

My problem is as follows. I can not compile my simple FPGA code (for example - writing some DIOs once) for sbRIO 9651(SOM) under LV 2016 because I get unroutable placement error - screenshot in attachment. In LabView 2015 I can compile code without errors. I have thought  that problem is in the CLIP which was generated on computer with Labview 2015 so I create new CLIP in actual computer with Labview 2016 based on previous CLIP but it didn't help. Error log indicates that problem is in a clock routing. In project are two derived clocks (27 MHz and 10 MHz) and they are exported to CLIP by some lines (DIO_81, DIO_66, DIO_42, DIO_47 for 27 MHz clock and DIO_76 for 10 MHz clock). I am not sure how to interpret error log - this set of DIOs can not be used to export one clock signals...? But why LV 2015 claims that is OK? Compilation rules have changed? Anyone could have an idea how to solve this problem?

[nturley]

That's an interesting error. Can you send me the design? I can take a look at it in Vivado and see if I can figure out what's going wrong.

--Neil