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Switching clocks for SCTL

Greetings,

 

I'm looking for a way to be able to run a SCTL with multiple clocks (one clock at a time of course). i.e. allow the user to select the clock of choice during or before code execution with some form switch. 

 

Our custom PCB has a 40MHz and 100MHz external clock going in the SOM and I want to be able to select a clock without recompiling or manually rerouting the PCB tracks.

 

I've tried the 'Select' and a case structure function with the clock references but that won't cut it due to dynamic refnums not being supported. (see picture)

 

Maybe someone has some suggestions that don't require adding dedicated PCB switches.

 

 

 

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Re: Switching clocks for SCTL

The clock source for the SCTL will need to be constant at compile-time. However, there are some options you could try that might give you similar behavior to dynamically choosing the clock.

 

  1. Compile two different bitfiles, one with each clocking option, and dynamically choose which to load in your host VI.
  2. Create 2 SCTLs in your FPGA code that run simultaneously. Include logic in your code that allows you to choose which loop you care about and are getting data from.

Will

National Instruments

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Re: Switching clocks for SCTL

Hi Will,

 

I was hoping I can avoid these options especially copying code as it is not great for maintainability.

Does this mean that doing it in the FPGA it's impossible?

 

I've spoken to some colleagues that used to do similar practices on VHDL with clock multiplexing.   

 

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Re: Switching clocks for SCTL

Could you compile at 200 Mhz and then run when needed? Since 200 is evenly divided by the two? 

 

I looked at clock multiplexing and this doesn't seem trivial. It could be worth reviewing for feasibility, I've never done it but it seems very interesting. 

 


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Re: Switching clocks for SCTL

Hi Terry, 

 

The code does compile for a 20 to 200 MHz frequency range from an external clock. I see this a possible solution if I'm using an internal clock.

However, if I go with your suggestion then I'd have to replace the 100 and 40 MHz clocks with a single 200MHz one and do some re-routing, I'm not sure after that if I need to be aware of any possible timing issues that could arise. 

 

I've heard about BUFGMUX for clock selection in Xilinx chips, not sure if we have access to that.

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Re: Switching clocks for SCTL

You won't be able to do clock selection via the BUFGMUX method directly in LabVIEW. However, this may be something you could implement yourself by modifying the CLIP.

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