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Is it possible to read Image Sensor using SBRIO 9651 or 9609?

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I need to get a small size picture at very high speed (128*128 or 64*64 @ 40000FPS), I only need to have the sum of all frame / the sum of successive frame different.


I already purchased a 1483 with flexrio 7976, I can get 128*128*12000 fps with camera link camera. it is fast, but not fast enough for us.


So I checked the image sensor itself, the image sensor is actually faster when we directly read from it, (without Cameralink in between), which is a good news for us.

(off the topic, the CXP version of the very same camera can also offer such performance, but NI doesn't have a CXP to FPGA adaptor😂)


But the problem is the sensor is outputting serial LVDS signal, I have checked the image sensor datasheet it says it can output up to 500Mbps at one LVDS port, while the image sensor can output at 40 LVDS port.


I checked FlexRIO 6587/6589, also other NI hardware, it seems to me I have to deal with this sensor with SOM 9651 or SBRIO 9609? Both of which have enough LVDS port. (9651/9609 have 48/45 pair of LVDS port)


But there comes the question, I have no idea about how can I use the embedded ISERDER in SBRIO/SOM, can anyone give me a hint?



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I recommend looking at this forum post. It provides some very useful links related to implementing internal SERDES on the 9651. 



However, one thing to note is that you won't be able to achieve the same rates on sbRIO as you would on FlexRIO. Our general guidance for the max achievable rate for differential I/O is 200MHz. This would likely be your limiting factor on the sbRIO products rather than the number or LVDS channels.



National Instruments

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Dear Sir:

Thank you for your advice!


I'm not sure 200MHz means in this situation, does it means I can get 200Mbit/sec at each LVDS port, or 200MHz*SERDERE depth? may be 1600Mbit/sec for each LVDS port?



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Accepted by topic author jiangliang

Hi Jiangliang


I've looked into your concerns some more and realize I was mistaken in my previous post. The 200MHz guideline mentioned in the linked page is a guideline for what is reasonably achievable for differential IO without significant effort to customize the CLIP. In your case you would in fact be making significant modifications to the CLIP by implementing Xilinx's ISERDESE2 and OSERDESE2 resources. This would allow you to reasonably achieve much higher rates and should allow you to hit the 500Mbps that your sensor can reach.


In addition to implementing the ISERDESE2 and OSERDESE2 resources you should also keep in mind that meeting timing requirements will be a concern at higher speeds. In your case it would likely be necessary to write some timing constraints by modifying the XDC file provided by the CLIP generation wizard. The purpose of this is to make sure the data you're outputting to the sensor meets it's timing requirements and the data being inputted from the sensor meets the Zynq's timing requirements.

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Just curious about whether you get a chance to successfully communicate through the LVDS lines to read/write image at 500Mbps rate?




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Message 5 of 11

Hi, Will


If I want to enable the communication between two 9651/9609 through SERDES LVDS lines, anything special I should pay attention to while make the PCB layout? I mean, for example, I have two sbRIO-9609 mount on a same PCB through RMC. I want to transfer high speed serial data between them, because of limited I/O pins available on sbRIO. Is this reasonable or possible? BTW, is there any recommendation on how to expanding more I/Os for sbRIOs?




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Regarding more IO, I just started using a MAX7301 to add IO. It looks promising in initial testing.

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Thanks for your suggestion. But MAX7301 is not fast enough. I need to communicate with some high speed A/D, which is doing 20MSps data acquisition. 🙂




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Message 8 of 11

Hi, Will,


If I use sbRIO-9607 and customize the CLIP to use SERDES resources, what kind of I/O speed would I expect to achieve?




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Message 9 of 11

Hi, Will


The reference page says the achievable frequency is 80MHz for SE cases. I'm wondering what kinds of things we should pay attention if I want to achieve like 8 lines parallel 60MHz data bus to transfer data? Besides, while the data bus is 60MHz, does that mean I need to feed out a 120MHz clock from master to slave to make sure the data could be sampled properly on the slave board?




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