Increase Depth Of Memory For Fpga

[lucamonopoli]

Good Evening,

attached in the PDF my Question

thanks

Luca

[tannerite]

Hi Luca,

Though the Zynq architecture may allow communication between the FPGA fabric (PL) and the memory interface, our software stack does not use the AXI interface to implement this type of functionality and it is not trivial for us to add this type of functionality at this point.

The only volatile storage accessible from the FPGA target within LabVIEW is what you have circled in the LabVIEW project.

We will continue to collect feedback like this for potential improvements in the future but we do not have any plans on implementing this feature at this time.

- Tanner

[lucamonopoli]

hi tanner,

thanks for your answer.

My suggestion is based on what i tested on my personal avnet zynq board.

i think, adding even in the future those capabilities for all zynq platform, is a great benefit.

The interface with the world on this platform could be of a big amount of datas.

it would be really helpfull to preprocess on the FPGA using high speed DDR buffering

i hope to see one day this improvement

regards

Luca

[tannerite]

Luca,

Where we really see the need is for vision-based applications. There are some of our products that have DDR memory accessible to the FPGA (e.g., FlexRIO) that many customers leverage for pre-processing.

The project manager has already been informed and we will keep this in mind when spec'ing future products.

- Tanner

[lucamonopoli]

ok thanks

[lucamonopoli]

this answer seems to be ok

https://decibel.ni.com/content/docs/DOC-41463

in the folder project miss 9651 example just compact rio

[lucamonopoli]

Hi is there

any news in order to do easily this job?

[nturley]

Yes! The news is that Host Memory Buffer is moving from Labs to being a native feature of RIO. It's very exciting. There are some caveats, we have some known issues to fix and it's only a handful of targets that support it, but 9651 is one of them. So you can try it out and see if it works well enough to be useful for you.

We exposed it as a "DRAM bank" and there's a new VI on the FPGA interface palette.

I'm giving a presentation about it at NIWeek tomorrow. I'll post my slides afterward so you can get the same information.

[nturley]

Here are the slides from the presentation on Tuesday.

[lucamonopoli]

Hi,
i'm very pleased and curious to see this.
it's very near of what i've imagined using High Performance port of Zynq
to DDR direct access for zero latency.

I appreciate of course FPGA Buffering for processing on it.

I appreciate also a lot the opportunty in term of PING PONG
strategy for RT <-> FPGA transfer for zero latency.

One question :
Any Degraded performance on Linux once this memory is allocated?

I would test as soon as receive DVD 2017.

GREAT JOB, in italy we say

"Lemon must be squeezed until the end "
Best Regards

LM