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FPGA compilation fail with vivado error DRC 23-20

I'm using SOM 9651 with a external clock, the program used to working until I add a derived clock from external clock.


Is it not supported by LabVIEW FPGA or SOM 9651? or maybe there is something I can do to fix this problem.


I made two simple SCTL with only the external clock driven loop, and a external derived clock driven loop, the issue is the same, can't finish compliation so there should not be something with my code, it might be some limitation with the SOM platform? 


The external clock is 100M, and the added derived clock is 25M.


Thanks, below is the error information.


LabVIEW FPGA: The compilation failed due to a Xilinx error.

ERROR: [DRC 23-20] Rule violation (PDCN-1568) BUFGCTRL_S_pins_both_connected_to_gnd - For cell window/Bufgce0/GenBufgCtrl.BUFGCTRLx placed at site BUFGCTRL_X0Y20 both S0 and S1 pins are tied to GROUND. Selection of an input clock requires a "select" pair (S0 and CE0, or S1 and CE1) to be asserted High. If either S or CE is not asserted High the desired input will not be selected. Please modify your design.

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Re: FPGA compilation fail with vivado error DRC 23-20

The behavior you're seeing is likely related to a known issue that is actively under investigation. I believe the CLIP generator will incorrectly assume that the derived clock is never ready, causing the design rule check error you're seeing. This can easily be fixed by editing the vhd file created from the CLIP generator. Find the LabVIEW Clock Port section of the VHDL and change the ready signal to '1' instead of '0'. Here's an example:

--LabVIEW Clock Port: ext_clk_pin36
ext_clk_pin36_lvc <= aDio_in(36);
ext_clk_pin36_lvc_ready <= '1';




National Instruments

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Re: FPGA compilation fail with vivado error DRC 23-20

Thanks a lot, I will give it a try later, I actually fixed this issue by flying a wire to make sure external sourcing clock is based on a SOM clock, which also can archive my goal.


Again, thanks for your fast response!


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