the questions is, how can we read LVDS signals with a voltage level of 1,8V at a frequency at 120MHz?
Please dont tell me this is not possible 😉
It should be possible through the FPGA. If there is a base clock of 40MHz, this can be increased by using a derived clock. A Single Cycle Timed Loop (SCTL) can be used to make the code more efficient from a timing perspective. Other strategies might be worth considering such as pipelining.
It is noted in the FPGA course that "not all FPGA VIs compile successfully with faster clock rates" than 40MHz which is what most FPGA VIs are designed to function at, however I have heard of applications with faster clock rates successfully implemented. Best thing is to try it! Maybe run it in a simulated execution mode first?
the 120MHz is not the problem... the problem is the standard of LVDS... our source and sink(there are several LVDS Pairs) are LVDS 1,8V and the Clip generator does not let me choose the LVDS_18, but only the LVDS_25!!! Thats the problem to deal with...
Can anybody help?
LVDS_18 is not supported by the FPGA on the SOM. This is why LVDS_25 is the only option listed in the spec document and CLIP generator.