Am I correct in saying the sbRIO-9651 does not support Analog Inputs?
The Xilinx Zynq FPGA has two 12bit ADCs with up to 17 differential inputs.
I could not see any of these inputs on the SoM connector.
You are correct in that the sbRIO-9651 does not support using the built-in XADCs. You can certainly built ADCs into your carrier board and interface with them through the DIO, however.
You can also take advantage of the Pmod connectors onboard the reference carrier board to have quicker access to Analog I/O during development.
Peripheral Modules (Pmods) - The Pmod standard is defined by Digilent, Inc and is used for small I/O interface boards that extend the capabilities of FPGA control boards. Pmods communicate with system boards via 6- or 12-pin connectors. The reference carrier board provides Pmod-compatible connectors to support quick connectivity to the Pmod ecosystem for prototyping and evaluating sensors, converters, connectors, and other devices. Refer to Digilent or Maxim for more information and available Pmods.
Though my above comment about not supporting the built-in XADCs is true as we have not tested them through the SOM connector and the pins that they connect to on the SOM connector were not meant to be XADC inputs, I wanted to be fully transparent with what is actually in the hardware.
First, Xilinx calls out pins AD0P/N through AD15P/N as being multi-function pins. The SOM uses them for single-ended DIO, but their functionality can also be changed in the VHDL to make them XADC inputs. Here is a screenshot of this Xilinx documentation:
Even though these pins support this functionality, that does not necessarily mean that all of these differential inputs are routed to the 320-pin SEARAY connector on the SOM. In fact, I have highlighted in green the only channels that are physically routed to the SOM connector, below:
The channels in red may be routed to the SOM connector but are routed to critical interfaces that can not be changed.
You can attempt to instantiate the Xilinx primitive to properly interface with the XADC. This is well-documented by Xilinx so refere to their documentation for the VHDL implementations needing to be added to the Socketed CLIP.
WARNING1: The lines that connect to the SOM connector are routed on the PCB as single-ended traces with series termination resistors of 24.9 Ohms. These are not routed as differential traces that the XADCs should be routed as. You will not have the benefits of differential signaling if you choose to use these. They may still fit your application needs, but you must realize that these lines are meant to be single-ended DIO rather than XADC differential inputs.
WARNING2: The XADC inputs take in a voltage between 0-1 Volts. Though Bank 0 is reference at 3.3 V, that does not mean that the XADC input range is 3.3 V!
WARNING3: National Instruments has not tested nor verified that this will work through the SOM connector; therefore, we can make no guarantees about the correctness of the data being read.
Thanks for this very detailed reply. I am interested in testing this functionality on my sbRio-9627 whilst I await the delivery of my 9651 as it affects our carrier board design. We would ideally like to use the XADC if we can get away with not having to include an external I2C or SPI interfaced ADC.
I have determined that the included analog inputs on the 9627 are achieved through the use of an externally multiplexed A/D rather than Xilinx XADC.
Could you please provide a similar table of pin routings between the 9627's 240 pin RMC connector and the relevant XADC pins on the Zynq 7020?
The sbRIO-9627 uses those ADC pins for internal functionality, so they are not accessible through the RMC connector.
Thanks. I spent a while trying to instantiate the XADC in VHDL without much success. Am I wasting my time trying to do this for the 9627 target? Will it never be able to compile?
Does anyone know how to utilise the sample VHDL from Xilinx to accomplish this? I managed to figure out how to generate the XML file the CLIP needs, however when compiling it fails, citing an error related to the I/O being unbound to socketed clip functions
I have attached the relevant VHDL files.