10-08-2007 04:38 PM
10-09-2007 02:52 PM
10-16-2007 03:56 PM
>Remote System>cFP-1808-PROT-I>cFP-CTR-502@2
>Type 1: Count Input>Count Input 0>
>Read Reset Mode Don’t Reset On Read
>Gate Source Gate Input 0
>Count Source 1 KHz Reference
>Terminal Count 10 *
* Rescale Frequency = 1 KHz / [(10+1)*2]
>Remote System>cFP-1808-PROT-I>cFP-CTR-502@2
>Type 1: Count Input>Count Input 0>
>Read Reset Mode Don’t Reset On Read
>Gate Source Always Enabled
>Count Source Previous Channel
>Terminal Count 119 **
** 120 counts in total due to 0 indexing
>Remote System>cFP-1808-PROT-I>cFP-CTR-502@2
>Type 3: Discrete Output>Output 0>
>Output Mode Toggle, Reset On
>Output Source Counter Channel 0
>Remote System>cFP-1808-PROT-I>cFP-CTR-502@2
>Type 3: Discrete Output>Output 1>
>Output Mode Toggle, Reset On
>Output Source Counter Channel 1
>Remote System>cFP-1808-PROT-I>cFP-CTR-502@2
>Type 3: Discrete Output>Output 2>
>Output Mode Toggle, Reset Off
>Output Source Discrete Data
Jing Zhang
Staff Scientist
ESP
EMCORE Corporation
10-16-2007 03:56 PM
Counter 0 is taking the 1KHz hardware clock as input. By setting the terminal count 10, the counter overflows and then resets every 11 (10+1) count.
By associating output 0 with counter 0, the output toggles every time counter 0 overflows. That is, when counter 0 overflows the 1st time, the output goes from High to Low. When counter 0 overflows the 2nd time, the output goes from Low to High.
By setting Counter 1 count source to previous, the counter increments each time counter 0 overflows. By setting the terminal count 119, the counter overflows and resets every 120 counts (0 indexing).
By associating output 1 to counter 1, the output 1 toggles each time counter 1 overflow.
By setting the gate source of counter 0 to gate 0, counter 0 is enabled when Gate 0 reads 1 and disabled when gate 0 reads 0.
Now, we route output 1 AND 2 to Gate 0. The truth table is:
Execution Step |
Output 1 |
Output 2 |
Gate 0 |
Counter 0 |
1 |
0 |
1 |
1 |
Enabled |
2 |
1 |
0 |
1 |
Enabled |
3 |
1 |
1 |
1 |
Enabled |
4 |
0 |
0 |
0 |
Disabled |
Initial State = 4.
Execution Step 1:
[SW] Writes Output 2 = 1 (TRUE)
[HW] Gate 0 = 1, counter 0 and 1 start counting
When counter 1 overflows and resets, output 1 = 1
[SW] Read from compact fieldpoint repeatedly, when Output 1 = 1, write output 2 = 0
[HW] Counter 0 and 1 keep counting. When counter 1 overflows again, output 1 = 0
[HW] Now, both output 1 and 2 False, Gate 0 = 0 (FALSE), counter 0 is enabled.
Jing Zhang
Staff Scientist
ESP
EMCORE Corporation
10-16-2007 03:57 PM
10-16-2007 04:03 PM
10-23-2007 04:35 PM
Hi Jing,
Thanks for posting your solution to the forums. It looks like you have provided an extensive breakdown of the Hardware and Software processes necessary to set up a finite pulse train with a cFP-1808 and a CTR-502 module. This should be helpful information for others who are trying to attain a similar behavior with these hardware devices.
Let me know if there are other specific questions on this topic that I can help with or clarify. Have a great day!
Jason W.