08-11-2008 09:26 AM
08-12-2008
11:16 AM
- last edited on
02-03-2026
03:03 PM
by
Content Cleaner
Hi guilio,
It looks like the FPGA will sample the 9215 at the programmed rate, and then the software loop will sample the data from the FPGA at a different rate. However, there is no buffering between the FPGA and the real-time VI. If you set the software loop at 100 ms and the FPGA at 1 ms, you will only get 10 samples per second in the real-time VI. I think the example attempts to oversimplify the FPGA programming unfortunately. If you want to get all of the samples, you will probably need to use a DMA FIFO to buffer the analog data between the FPGA and real-time (since the real-time loop will not be able to run anywhere near as fast as the FPGA). The following links will hopefully give you some insight:
https://forums.ni.com/t5/Example-Code/Use-DMA-FIFOs-to-send-data-to-and-from-an-FPGA-target/ta-p/352...
https://knowledge.ni.com/KnowledgeArticleDetails?id=kA00Z0000019LnBSAU&l=en-US