The example projects attached to this document provide Tri-Mode (10M/100M/1G) Ethernet connectivity on the SFP+ ports of the NI PXIe-6592R High Speed Serial Instrument, and the NI 7932R/7935R Controller for FlexRIO. The example projects support the 1000BASE-X and the SGMII standards on the SFP connectors, with 10M/100M/1000M speeds in case of SGMII. Connecting to an Ethernet network requires a media-specific SFP transceiver module installed in the SFP connector, supporting the 1000BASE-X and/or the SGMII standard on the SFP connector.
Hardware and Software Requirements
The following modules are supported:
LabVIEW 2016 SP1 (32-bit)
LabVIEW FPGA 2016
NI PXIe-6592R: NI LabVIEW 2016 Instrument Design Libraries for High Speed Serial Instruments 16.1
NI 7932R/7935R: FlexRIO Support 16.1
The example projects use a custom FPGA CLIP. The CLIP implements the Ethernet MAC and the interface between the MAC and the SFP connector using the Xilinx Tri-Mode Ethernet MAC IP and the Xilinx Ethernet 1000BASE-X PCS/PMA or SGMII IP (refer to the CLIP top-level vhdl file comments for the IP versions used, and the configuration options used for these IPs). The projects also contain logic implemented on the FPGA for accessing the installed SFP transceiver modules through the SFP Serial ID interface (described in the SFP MSA Appendix B4). The Serial ID interface can be used to identify the installed transceiver module, and depending on the transceiver module, to configure/monitor ASICs located on the transceiver module, such as the physical layer IC (PHY) translating the data between the SFP connector and the optical or copper cable (the example projects demonstrate the configuration of the Marvell 88E1111 PHY in case it is accessible through the SFP Serial ID interface at the device address 0xAC).
The projects also include a host support library (TriModeEthernet support.lvlib) providing VIs for initializing, configuring and monitoring the status of the ports, accessing the registers of the IPs used in the CLIP, and accessing the SFP Serial ID interface. For more information refer to the context help of the library and the library VIs.
The projects are created from the 1G and 10G Ethernet sample projects shipping with the NI LabVIEW 2016 Instrument Design Libraries for High Speed Serial Instruments 16.1, therefore the project structure is almost the same.
There are three top-level FPGA VIs:
TriModeEthernet_FPGA.vi: Implements transmit/receive on all ports of the device.
FPGA Top - Packet RX Only.vi: Implements only the packet reception on Port 0 of the device.
FPGA Top - Packet TX Only.vi: Implements only the packet transmission on Port 0 of the device.
There are five top-level host VIs:
Getting Started (Loopback Test).vi: Loopback test using the FPGA personality provided by the TriModeEthernet_FPGA.vi top-level FPGA VI.
Getting Started (RX on FPGA).vi: Packet reception only using the FPGA personality provided by the TriModeEthernet_FPGA.vi top-level FPGA VI.
Getting Started (TX on FPGA).vi: Packet transmission only using the FPGA personality provided by the TriModeEthernet_FPGA.vi top-level FPGA VI.
Packet TX Only.vi: Packet transmission only using the FPGA personality provided by the FPGA Top - Packet TX Only.vi top-level FPGA VI.
Packet RX Only.vi: Packet reception only using the FPGA personality provided by the FPGA Top - Packet RX Only.vi top-level FPGA VI.
Additional Information or References
The examples were tested using the following SFP transceiver modules:
SFP transceiver module
Copper, supports SGMII with auto-negotiation only.