Examples and IP for Software-Designed Instruments and NI FlexRIO

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SPI IP

spi.png

SPI IP »

This IP implements serial peripheral interface (SPI) communication, including support for both master and slave functionality.

Description: Serial Peripheral Interface (SPI) buses are commonly used to communicate between a controller (master) device and a target (slave) device. In general, SPI buses require four lines for communication: chip select/clock enable, serial clock, master serial data out (MOSI), and master serial data in (MISO). In some cases only a subset of these lines are used; some devices multiplex both MOSI and MISO onto a single bidirectional data line. This IP includes LabVIEW FPGA code for both an SPI master and an SPI slave.

Additional Documentation:

  • After Installation - C:\Program Files (x86)\National Instruments\LabVIEW 2012\user.lib\_NI SPI IP\documentation\NI 5644R Serial Peripheral Interface (SPI) Example.pdf

Compatibility:


Dependencies:

  • none

Performance:

  • 3 and 4-wire interfaces
  • Up to 64 bit word lengths
  • Programmable clock frequency

FPGA Footprint:

Xilinx Virtex-6 LX195T

  • 0.6% / 783 LUTs
  • 0.5% / 1182 Flip-Flops
  • 0.0% / 0 Block RAMs
  • 0.0% / 0 DSP Slices
  • 200 MHz clock rate

Latest Version:

Previous Versions:

  • none available

Note: All source on this community is distributed using VI Package Manager (VIPM). For more details on VIPM, please read A Note on VI Package Manager

Ryan Verret
Product Marketing Engineer
Signal Generators
National Instruments
Contributors