NI DRAM Packetizer IP

[Example_and_IP_Admin]

Overview

Some data transmission protocols, such as VITA49, require that each data packet contain only samples from one channel.  However, many multi-channel FPGA IP components process data in an interleaved manner.  This motivates the development of a component that is capable of receiving interleaved multi-channel data and transmitting packetized data. Due to its high throughput and large capacity, dynamic random access memory (DRAM) is used to solve this problem.

Software Requirements

• LabVIEW 2014 or later
• LabVIEW 2014 FPGA Module or later
• NI FlexRIO 14.0 (or similar) or later

Hardware Requirements

Any NI FPGA target that includes a 512-bit DRAM interface is supported.  This includes, but is not limited to the following targets:

• NI PXIe-7972R/7975R/7976R FlexRIO
• NI 7931R/7932R/7935R Controller for FlexRIO
• NI PXIe-5624R IF Digitizer
• NI PXIe-5170R/5171R Reconfigurable Oscilloscope
• NI PXIe-6591R/6592R High Speed Serial Module

Current Version

NI DRAM Packetizer IP 1.0.0»

FPGA Resource Utilization

Slice Registers	18,000 (3.5%)
Luts	18,000 (7.1%)
BRAMs	43 (5.4%)
DSP48E1s	0 (0.0%)

[Guillaume_B]

Hi,

Thank you for the IP. Is there a way for you to modify the IP to map to 256 bits memory DRMA like USRP-RIO ?

Regards,

GuillaumeB

[Terry_ALE]

There is a DRAM API that supports 256-bit width. See: <LabVIEW>\instr.lib\FlexRIO\DRAM FIFO\v2\FPGA\DRAM FIFO