The JESD204B Simple Streaming sample project demonstrates how to use Xilinx JESD204B IP with NI PXIe-6591R card. Use DMA FIFOs to stream data between the Host and FPGA. Store the stream data either in BRAM (internal memory) or DRAM (External memory). Transmit or receive this stream data to/from external JESD204B compliance devices via Xilinx JESD204B IP at 12.5Gbps on Port0 and Port1.
This project contains four top-level host VIs:
The NI PXIe-6591R IO Socket CLIP connects the JESD204B protocol IP to the top-level IO signals, including the Multi-Gigabit Transceivers (MGTs).
Note: When PXIe-6591R card is looped using Mini-SAS Loopback adapter at Port0 or Port1, append “-Port0 to Port0” (or) “-Port1 to Port1” to L-M-F-S mode depending on the connection made (say “4-2-2-2-Port0 to Port0”).
I would like to adapt the RX sample project to receive data from a different device. To which Signal on the DDC connector is the JESD204B SYNC Signal routed?
In the documentation for the RX sample Project testing with ADC12J4000, a "NI MiniSAS to FMC interposer board" is mentioned`, but I could not find documention or a source to order this board.
Is there an overview of the required modifications to adapt the code to a different frame / line rate and a different frame format (e.g. 5 octets / frame)?
To which Signal on the DDC connector is the JESD204B SYNC Signal routed?
If you take a look at the top level vhd in the JESD CLIP you'll find the info you're looking for. If you extract the zip you can find it at the following location,
NI PXIe-6591R JESD Sample Project\JESD Sample Project\JESD204B Simple Streaming\CLIP\JESD204B_NI_6591R.vhd. Once you open it up you'll find the following info on line 2363.
-- Rx SYNC out signal DDC_GPIO_Out(0) <= rx_sync_from_core_r; DDC_GPIO_OutEnable_n(0) <= '0';
In the documentation for the RX sample Project testing with ADC12J4000, a "NI MiniSAS to FMC interposer board" is mentioned`, but I could not find documention or a source to order this board.
My apologies, but mention of the interposer was supposed to be removed from the documentation since it isn't publicly available. I'll look into having the example updated to reflect that.
Is there an overview of the required modifications to adapt the code to a different frame / line rate and a different frame format (e.g. 5 octets / frame)?
If you open the simple streaming example the host vi should have some controls that allow you to modify the line rate and LMFS. Setting up the 6591 in a loopback configuration would be a good place to start when investigating these settings.