Channel Emulation Example for the NI PXIe-5644R »
With a DSP-focused FPGA coupled to both RF input and RF output, the NI PXIe-5644R makes an ideal hardware platform for an RF channel emulator. This example implements inline, real-time DSP to apply arbitrary channel models to the RF data.
Description: This example uses the NI PXIe-5644R VST to emulate the over-the-air (OTA) channel for a wireless communication link. The wireless channel emulator is based on the VST streaming sample project. By combining floating point host code and fixed point FPGA code, the channel emulator provides flexible channel profiles and models that can be easily added and/or modified. It provides two custom channel profiles which are deterministic and stochastic with multiple input multiple output (MIMO) configurations. The channel emulator example can be run as is, or extended to more sophisticated models. In addition to the channel emulation IP linked in the dependecies section, this example includes fixed-rate resamplers to convert the 120 MS/s VST I/Q rate to 100 MS/s, supporting channels up to 80 MHz wide.
Xilinx Virtex-6 LX195T
Note: All source on this community is distributed using VI Package Manager (VIPM). For more details on VIPM, please read A Note on VI Package Manager
Is there a 2015 port for this available?
We don't have a 2015 version of this yet, but we do have an engineer looking at what it would take to get it updated. I hope to have an update for you within a few days.
I just posted the LabVIEW 2015 version. Thanks for your patience!
I think there is something wrong with the VIPM file for 2015.
The vipm://national_instruments_lib_ni_channel_emulation_example_for_the_ni_pxie_5644r-22.214.171.124 is trying to install into LV 8.2?
8.2 is the default setting for the LV version in VIPM, before VIPM is able to resolve the information from the VIP.
In this case the link requires VIPM to load the VIP from the NI FTP server, before VIPM can extract the information from the VIP. The error message indicates that VIPM is not able to access the NI FTP server to retrieve the VIP file for this package.
I just tested the same link and it worked for me. Please try again and make sure you are connected to the Internet at the time.
I tried from my laptop and desktop with the same error. They are on the internet; although the customer I am supporting for this does not have their LV PCs on the network.
I have VIPM 2014 installed.
I just tried installing the 2012 version and it installed as it should.
Could have something to do with being within NI's network and outside? First time I am seeing this.
I have seen issues accessing the Tools Network Repository when connected to the NI wifi within a virtual machine instead of over our wired connection. Could this be the issue you're running into?
On a native OS (Win 7 64 bit), no VM, trying to install to LV 2015 32 bit.
Is there a way I can manually download the package:
Ultimately my customer will want to download it for PCs that are offline.
I was sidetracked by other tasks but finally got to this and was able to get it to download and am doing a test compile. Thank you!
Opened \LabVIEW 2015\examples\NI Channel Emulation Example for the NI PXIe-5644R\MIMO Channel Emulator (NI PXIe-5644R).lvproj
Tried to compile the FPGA and received a timing error:
re-ran compile and it worked.
I have test compiled this a few times on a few machines as well as on NI's cloud compile. Some pass, some fail to compile. Has this been observed by anyone else? I wonder if this is a function of when the design is bigger you could get failures. If that is the case maybe the FPGA tool could remember what worked before and try those as starting points?
The FPGA is so full in this design that we see less than a 50% compile success rate, so you're not alone in the results you get. If you're compiling on the cloud, I'd recommend kicking off several compiles in parallel to help ensure you get a good one back.
If you're compiling on the cloud, I'd recommend kicking off several compiles in parallel to help ensure you get a good one back.
Jon, thanks for the response. How do I run several compiles of the same FPGA VI in parallel? Do you mean from multiple machines? I did a scan of the literature and I know can compile different FPGA VIs at the same time but do not know how this can be done for the same FPGA VI from the same PC.
You have to create multiple build specs. If you're on LabVIEW 2014 or later, you can then right click and those build specs and select "build all" (or something similar). If you're on an earlier version, you need to wait for the intermediate files to generate before you can kick of another one.
Do you know if this works with the 5646R? Is there a way to get this ported to the 5646R?
I tried to run this with 2 VSTs but I encountered an error.
If I choose just 1 Tx and 1 Rx antenna, the code runs fine without errors.
But if I choose 2 Tx or 2 Rx antennas, I'm encountering an error - seems like an overflow.
Here's a screenshot of the error:
After I click start, 'DMA1 FIFO Space Left' will drop from 500k to 0 quickly and then the error will appear.
Has anyone faced this issue before?
We've figured out why the error was happening.
It is due to slot bandwidth of the chassis.
We were using a PXIe-1075 with the 2 VSTs using the same switch.
So we moved 1 VST to another slot and now it works fine.
Has anyone got a FIR6o5.coe and a FIR5o6.coe file? Thanks a lot!
Anyone who is interested in using this example with the 5645R please see the following link
I changed the project, and then recompiled to make it compatible with this card
Have any of you tried to reconfigure this project to run on VST 5646R?
Any version of this example ported to 5646?