This example program implements Aurora 64b66b streaming through the Nanopitch connector and MGTs on Ultrascale FlexRIO instruments such as the PXIe-7915 FlexRIO Coprocessor. This includes an example socketed CLIP for the Ultrascale FlexRIO MGT socket, which can be built upon for other applications utilizing the Ultrascale FlexRIO MGT or Nanopitch connector for high-speed serial data communication. The Aurora streaming implementation in this example is also compatible with the Aurora implementation used in the NI Streaming 5840 Host example available through VI Package Manager.
This example implements a single four lane wide Aurora 64b/66b core on the MGT of a PXIe-7915 FlexRIO Coprocessor. The project contains 3 top-level host VIs:
and one top-level FPGA VI:
The example implements an AXI4-Lite streaming interface to communicate between the LV FPGA block diagram and the Aurora core in the socketed CLIP. The example includes the capability to generate several test patterns: a ramp signal, count up, count down or PRBS. It also demonstrates generating IQ data of an arbitrary rate and frequency on the FPGA meant to be consumed by a PXIe-5840 VST along with the NI Streaming 5840 Host example.
This example includes a pre-compiled bitfile for the PXIe-7915 coprocessor. All host VIs are configured to use this pre-compiled bitfile so the example can be run without any compilation required. If running the example along with the NI Streaming 5840 Host example, use a Nano-Pitch cable to connect the PXIe-7915 and PXIe-5840. The 5840 project includes several host VIs that implement Aurora streaming which are compatible with this example's implementation, e.g. if using the Aurora Receive to RFSG host VI, the PXIe-7915 should transmit data via Aurora.
For further details on the Aurora protocol, refer to the Xilinx Aurora 64B/66B LogiCORE IP Product Guide. This .xci file used to configure the Aurora IP cores in this example is also now attached as a second .zip file to enable users to customize the Aurora configuration more easily. Any changes to the Aurora IP would also potentially require re-interfacing the IP with the existing CLIP and LabVIEW FPGA.