Example Code

Using Block Memory as a Circular Buffer in LabVIEW FPGA

Products and Environment

This section reflects the products and operating system used to create the example.

To download NI software, including the products shown below, visit ni.com/downloads.

    Software

  • LabVIEW FPGA Module
  • LabVIEW

Code and Documents

Attachment

Overview

Data acquisition applications can sometimes require buffered acquisition, which stores a certain number of samples in a circular buffer that are only stored to file or analyzed when a certain condition is met. For large buffered operations on FPGA targets, using FIFO memory and look up tables may not offer a large enough storage space. This example demonstrates the logic for using block memory to act as a circular buffer for FPGA.

 

Description

The circular buffer is made using a block memory with size of 6,000 32-bit integer elements. This sample program generates an array of 20,000 incremental values which are read one by one into the block memory until the specified value is detected as the current element the array. This operation simulates a stop condition of data acquisition or analysis. The acquisition will end, and the values will be read back for the previous 6,000 data points. These are read sequentially, recreating the 6,000 buffered points acquired before the stop condition.

The two graphs on the front panel demonstrate the 6,000 values read back from the block memory and the order of the addresses used to create the sequential read operation. This project contains a simulated cRIO and FPGA, but the code will run on your development machine.

 

Requirements

  • LabVIEW 2013 (or compatible)
  • LabVIEW  FPGA Module 2013 (or compatible)

 

Steps to Implement or Execute Code

  1. Download both the VI and project found below.
  2. Open the Test Buffer LabVIEW Project and the Address Test VI.
  3. Enter a desired value into the numeric control (anything between 0 and 20,000 will return valid results).
  4. Run the VI to simulate the FPGA operation and populate the graphs.

 

Additional Information or References

Front Panel

Example Front Panel.PNG

Block Diagram

sni.png

External Links

What is the Maximum Size for FIFOs in LabVIEW FPGA?

 

 

 **This document has been updated to meet the current required format for the NI Code Exchange. **

Example code from the Example Code Exchange in the NI Community is licensed with the MIT license.