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Three (3) Examples of Exporting a Clock Signal on an FPGA Device

Introduction

The following example outlines three individual methods for exporting a clock from an FPGA device. This example project was prepared using a PCI-7831R; however, may be employed on any FPGA reconfigurable hardware. The methods allow users to create a clock signal on a FPGA digital output line. The examples demonstrate the use of FPGA derived clocks, Signal Generation Express VIs, and PWM generation techniques.

Steps to Complete

1. FPGA Derived Clock Exported via Logic Not

a. Create a Single-Cycle Timed Loop (SCTL)
b. Place a Boolean constant outside the loop, to initialize the clock edge.
c. Place a 'Not' function inside the SCTL.
d. Use a shift register to continually update the boolean output.
e. Use a FPGA I/O node to write the digital channel.
f. Double-Click the SCTL to configure the desired derived clock. Remember the SCTL will execute with a period of 1/2 the derived clock rate.

2. Export Boolean value from Square Wave Generation Express VI

a. Create a SCTL.
b. Place the Square Wave Generator inside. Functions>>FPGA Math & Analysis>>Signal Generation
c. Configure the Express VI to run 'Inside a SCTL.'
d. Create controls for clock specifications.
e. Use FPGA I/O node to write digital channel.

3. Use PWN Generation algorithm to Export Clock

a. Create a SCTL.
b. Place the PWM Out-FPGA SubVI.
c. Wire controls for clock specifiactions.
d. Use FPGA I/O node to write digital channel.

Block Diagram and Project.jpg

ExpressVI Config.jpg

Configure Timed Loop.jpg

Front Panel.jpg

Additional Notes

For additional assistance with specific LabVIEW functions, please use ctrl+h to view the Context Help dialog.

Patrick Corcoran
Application Engineering Specialist | Control
National Instruments

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