Overview This example shows how to combat channel switching caused by FPGA FIFO overflow.
Description When sending multiple channels of data over an FPGA FIFO it is common to interleave the data. Unfortunately, if an overflow occurs, channel switching can also occur, as the interleaved data is decimated in the wrong order. To combat this the data from multiple channels can be combined together into one larger element. Whilst this method does not prevent data loss (see articles on increasing FIFO size and depth for help with this matter) it does mean that if overflow occurs, channel switching is prevented as all data points will be removed.
LabVIEW 2012 (or compatible)
Steps to Implement or Execute Code
Add Real-Time device and FPGA target to the project (If the device is not available, a simulated one would also work).
Run the VI. (If the simulated device is used, then the VI needs to be dragged from the Real-time target to "My Computer" in LabVIEW Project Explorer.)
Additional Information or References VI Block Diagram
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