Overview This example demonstrates the use of pipelining in LabVIEW FPGA and illustrates a comparison of clock cycles between a standard loop and a loop implementing pipelining techniques.
Description This project uses a CompactRIO with an analog input module and an analog output module. It contains two separate FPGA VIs. One VI uses standard practices while the other incorporates pipelining techniques. They both read from four analog channels, perform a random scaling operation, and output to four analog channels with a benchmarking clock running in parallel. Each individual VI should be run separately and interactively to observe the differences in the number of clock cycles it takes to run each program.
The program can be modified for any FPGA hardware but results may vary.
LabVIEW 2013 (or later)
LabVIEW FPGA Module 2013 (or later)
NI-RIO 13.0 (or later)
cRIO-9014 (cRIO controller)
cRIO-9113 (cRIO chassis/FPGA)
NI 9201 (analog input module)
NI 9263 (analog output module)
Steps to Implement or Execute Code
Download the appropriate version of the code.
If using a similar hardware setup:
Open the project and configure the target IP (skip to step 4)
If using different hardware:
Open the project and add a new target
Drag the two VIs under the new FPGA target
Configure the input/output nodes to match the new target configuration
Compile if necessary (pre-compiled bitfiles are included for this setup)
Open each Block Diagram and observe the difference in implementation
Run the Standard.vi and note the clock cycles on the Front Panel
Stop the Standard.vi and run the Pipeline.vi. Compare the clock cycles between the two and stop the VI when done
See the LabVIEW FPGA Module Help or LabVIEW High-Performance FPGA Developer's Guide for further details on this, or other advanced FPGA techniques, as well as general FPGA coding practices
Additional Images or Video
**This document has been updated to meet the current required format for the NI Code Exchange.**