cRIO data logger with GPS synchronisation and timing

[NickWill]

Overview

cRIO based datalogger, with sample timing taken from GPS synchronised Timekeeper

Description

Here is an example of one method of generating sample data from a successive approximation ADC based C-series module, with sample timing derived from GPS.

Using a 9467 GPS module to discipline a Timekeeper on the FPGA, data is read back at the prescribed rate. This is passed up to a host PC for logging. Control and status information can be passed back and forth between the host and the RT target.

This is work-in-progress and the ultimate aim is to make it easily scaleable to many cRIOs. I'll also add local logging options as well as host-side logging.

Please leave any feedback for additional features.

Steps to Implement or Execute Code

     The attached project is written in LabVIEW 2013. If you open the project you can see the hardware it is currently targetting. I currently have a 9467, 9215, 9403 and 9263 in a 9118 backplane and a 9022 controller.

     The code makes use of the fxptosgl reference design and the Timekeeper example code. All of the required code is included but it is recommended that the tools are downloded and added to your user.lib folder.

Requirements

Software

LabVIEW 2013

LabVIEW RT module

LabVIEW FPGA module

Hardware

cRIO chassis

9467 GPS module

Analogue input module such as the 9215 or 9220

other hardware is optional and the functionality has been included for completeness

[pepe70]

Hello NickWill

Is it possible to get the above code for Labview 12?

Thank you in advance

[NickWill]

Hi pepe70,

I have tried to save it back to 2012 but it has a whole bunch of elements that don't exist in 2012. It would take a while to get it to work but I can't even check 2012 code other than by loading it in 2013 again.

Interestingly, as the dependencies to the Timekeeper code exist under my user.lib folder, it insists on saving them for a previous version too. It can't do this however as it needs the password to access the block diagram and I don't have that. The only option for exporting was to change the code to point at a copy of the timekeeper library under vi.lib instead. That folder is excluded when saving for a previous version. The export then ran through but warned of many changes in the exported version, connections broken etc.

This code needs more work in any case. I had used network streams for speed, but I'm going to change it to used managed lower-level TCP connections. I've written some code for the comms already and it will allow for any number of targets in addition to managing disconnections gracefully. These changes may also mean that I can save it to an old version of LabVIEW more easily. I hope I'll get the chance to re-visit the code in the next few weeks. If I do I'll give it a go and add any info here.

In the meantime, have a look at the FPGA Timekeeper itself as the example code that comes with it for the cRIO is very easy to use and provides the basis of whatever timing control you need.  If you are using the delta-sigma 24-bit modules, you start having to get clever as they run on their own oversample clock but, for the normal 16-bit modules, you can easily time the acquisition using the timekeeper time and write to a simple, local, binary file.

Cheers,

NickWill

[Maloya]

Hello NickWill,

I try to use your Project using a Crio 9074, NI 9467 and LV 14. How do I get started?

How do I add the lib to my user.lib and finally use it. I'm knew to Crio.

Best Regards

[NickWill]

Hi Maloya,

I think the project contains everthing you need but there are elements I used such as the Timekeeper and fxptosgl which are reference designs that you can download separately. They can be found here https://forums.ni.com/t5/Sync-Labs/NI-TimeSync-FPGA-Timekeeper-Getting-Started/td-p/3543895 and here https://www.ni.com/en/support/documentation/supplemental/21/fixed-point-fxp-to-single-sgl-conversion.... They give you instructions on installation for each component.

The latter is a little redundant as you can now convert to SGL representation on the FPGA but I still prefer it as it gives you control and allows you to conbine the measurement data with details of its origin.

I'm afraid this code still uses network streams but it's okay for one or two targets.

If you are new to cRIO, this probably isn't the best place to start. You will need add your target to the project and copy over all of the code, FIFOs etc. Remember to point the FPGA call at the correct target and set the host to talk to the cRIO you are using.

Also, make sure you have added the required support onto your cRIO (use MAX and add software to the cRIO including network streams and so on)

Hope this helps

[Harss]

Hi,

Thanks a lot for the explanation.

Can I use this code for the following settings

1:NI Crio-9030

2:Analog input - NI 9223

3:GPS module - NI 9467.

Thanks.

[Harss]

Hi Nickwill,

This code seems to be really useful for me. I just had a question I am using NI 9223 for data acquisition and wish to acquire samples at the rate of 1 MS/sec. I need to use 'User Controlled I/O Sampling' . The 'NI 9223 User Controlled I/O Sampling .lvproj' which is already available in the Labview 2014 examples section. I am using NI 9467 for GPS timestamping.

Could you please recommend if I can use this code or any means by which I can modify that code to fit this timestamping code into it .

Thanks.

Regards.

[TinoMK]

Hi Everyone,

I am also trying to sync couple of crio's 9063 by using the GPS 9467 modules and timekeeper vi's.  I am using 9239  modules for analog acquisition.   I plan to use the pps signal as trigger and later in the rt part the timekeeper ns value to time stamp the data. Any other ideas for different approach ? What do you think? Thanks

[Harss]

Hi Tino,

You can use the 'FPGA Timekeeper VI'

Step1:'Use Get Time.VI' procedure provided in that example you can use the code which is already provided as an example

Step2: The 'Get Time.VI' returns the time as unsigned 64 bits

Step3:You may use a 'Local FIFO' to fill the time stamps into this

Step4:Just find out the resolution of your ADC , does it return Fixed Point values?

Step5:You can then either split the bits acquired from the timestamps and the ADC so as to transport them onto the RT.

Just check if this information is sufficient . I have created a similar application just let me know if you require some more info about it.

Regards