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Configuring the Gain of the NI 5761

Overview

The Socketed CLIP for the NI 5761 provides access to a SPI Engine, which can be used to write and read configuration registers on the ADC of the NI 5761. In this example, I configure the registers that control the gain of the ADS62P49 ADC on the NI 5761.

Description

The NI 5761 uses two Texas Instruments ADS62P49 ADCs. One for channels 0 and 1, and another for channels 2 and 3. Channels for each ADC can be configured with separate gain, but in this example, we will be configuring both channels together.

The register address 0x55 is used for specifying signal gain and time offset. The 4 most significant bits configure the gain from 0dB (0000) to 6dB (1100) in half dB increments. We will be writing to these bits.

To enable writing to registers, we need to write to address 0x00 a value of 0. To enable reading of a register, we need to write to the same address a value of 1.

The steps for any read write operation are:

  1. Wait for SPI Idle to be true
  2. Write the address and write data if applicable
  3. Wait for SPI Idle to be false
  4. Wait for SPI Idle to be true
  5. Read the data if applicable

In the example code, the SPI Engine loop automatically takes all of these steps. The engine will also automatically write to the 0x00 address the appropriate value depending on if you are choosing a read or a write operation. This SPI Engine code is based off the Configure ADC example project for the NI 5752.

On the host side, the user should write the address and the data, and then write true to SPI Start to start the operation.

The host side code used in this example uses the same code found in the 5761 Getting Started example project to acquire data from the card.

The ADS62P49 has many other configureable options. Documentation for this can be found on Texas Instrument's website.

Please note: NI does not test alternative configurations of the ADCs on the 5761. While you can configure the settings on the ADC, this may lead to unwanted results and behavior that is not supported.

Steps to Implement or Execute Code

  1. Download the attached ZIP file and open the project
  2. The project is configured for use with a PXIe-7975. If you are using a different FlexRIO card, add in the appropriate target to the project and recompile the FPGA VI.
  3. On the host VI, be sure to change the configuration of the Open FPGA VI Reference if you are using a different target.
  4. On the host VI, select the appropriate RIO Resource. Next, select the ADC for the channel you are acquiring on, and the gain. Lastly, configure the options for the data acquisition.
  5. Run the host VI. First the FAM will initialize. Then the ADC will be configured. Lastly, the data will be streamed.
  6. You can re-run the host VI with different gain settings. 6dB should double the voltage.

Requirements

Software

LabVIEW 2014 SP1

Hardware

NI 5761



Daniel C.
Applications Engineer
National Instruments
Contributors