Example Code

Viterbi Decoder

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Overview

This example implements a hard decision based Viterbi decoder on an FPGA bitstream file.  It retreives decoded bitstream data from the FPGA and pushes data back to the FPGA.

Description

Viterbi decoders are used in systems where data are transmitted and subject to errors before reception. For example, wireless transmissions are prone to error before reception so it is typically seen in applications like digital video, radio, mobile communication, and satellite communication.  Specifically, a Viterbi decoder is a method that uses the Viterbi algorithm for decoding bitstream files that have been encoded using an error-correcting code called convolutional code.  Convolutional encoding is a forward error correction technique that is useful in applications where the transmitted signal is corrupted by additive white gaussian noise.  Additive white gaussian noise appears normally in wireless transmissions.

Convolutional codes are usually described using two parameters:

  1. The code rate (r): "k/n" is the ratio of the number of bits into the convolutional encoder (k) to the number of channel symbols outbut by the convolutional encoder (n) in a given encoder cycle.
  2. The constraint length (K): "K" is the length of the convolutional encoder - how many k-bit stages are available to feed the combinatorial logic that produces output symbols.

Viterbi decoding has the advantage of fixed decoding time and is well suited to hardware decoder implementation as seen in this example.  But since computational requirements grow exponentially, which causes this to be a resource intense decoding method, it is normally limited in practice to constraint lengths of K <=10.

In addition, convolutional code can be described by generator sequences that are the impulse responses of each coder output branch.  Generator sequences specify convolutional code completely by the associated generator matrix.

Hardware Viterbi decoder for basic code usually consists of three major blocks:

  1. Branch Metric Unit (BMU) - used to calculate branch metrics or normed distances between every possible symbol in the code alphabet and the received symbol.  This block determines if  the decoder is a soft decision or hard decision decoder.  A hard decision decoder receives a simple bitstream file on its input and a Hamming distance is used as a metric.  A soft decision decoder receives a bitstream containing information about the reliability of each received symbol.
  2. Path Metric Unit (PMU) - used to summarize the branch metrics to get metrics for 2^(K-1) paths where one of the paths will be chosen as the optimal.  It is here that the trellis diagram of the code is referenced.
  3. Traceback Unit (TBU) - used to restore, as close as possible, the maximum likelihood path from the decisions made in the PMU.

In this specific example, this decodes a rate (r) =1/2 convolution code with a constraint length (K) = 7 and programmable generator matrix.  The example uses a programmable generator matrix to specify the convolutional code in the FPGA VI and decode the code in the Host VI.  It is a hard decision Viterbi decoder.

Steps to Implement or Execute Code

  1. Open PXIe5641R Viterbi K7 (FPGA).vi
  2. Press Run in the PXIe5641R Viterbi K7 (FPGA).vi
  3. Open PXIe5641R Viterbi K7 (HOST).vi
  4. If a different generator matrix is desired then change the values for the "Generator Matrix" control
  5. Press Run in the PXIe5641R Viterbi K7 (HOST).vi
  6. Observe the error of the output values received from the Viterbi decoded bitstream file.

Requirements

Software:

Hardware:

  • PXIe-5641R

**This document has been updated to meet the current required format for the NI Code Exchange. For more details visit this discussion thread**

Example code from the Example Code Exchange in the NI Community is licensed with the MIT license.

Comments
Member
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There is no Zip file attached along with.,

Please do upload the Zip file

NI Employee
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Hi Kalyan,

You can find the example at ni.com\labs under LabVIEW FPGA RF Communications Library.

This is free for download.

 

--NI RF Group

Member
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Dear NiRF Group,

 

Thanks a lot for the link

 

Regards

Kalyansuman

Member
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i am writing a my own fpga code .....so  i allways connect to fpga target......plese give me  a solution ....for developing a my own fpga codes ......

Member
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Hi! I've been trying to run this code for ages but the decoded bit always seems to be FALSE. I'm using the Viterbi Decoder [171 133] and trying to run the VI continuously (after resetting and asserting the INPUT VALID input). Please help. I seem to be doing something wrong. Thanks very much!

Member
Member
on

Please refer to the example attached to this page, regarding how the bits need to be packed and how to use the Viterbi decoder. Hope this helps.

Member
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on

I need to perform 3/4 depuncturing on my stream first and then pass perform viterbi decoding. Can this code accept a depunctured stream? How can I modify it?

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