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The attached project is showing a UART (Universal Asynchronous Receiver Transmitter) implementation on FPGA.
For better understanding how a UART works take a look at the UART 8N1 Simulation.vi.
This project is configured to work on cRIO-9024 with NI 9118 backplane and NI 9401 DIO module.
With some small changings the example is also running on R-Series, sbRIO or other NI FPGA targets with DIOs.
All VIs for UART you find in UART 8N1 (FPGA).lvlib.
Additional you can find the UART 8N1 Simulation.vi running on My Computer.
Steps to Implement or Execute Code
1. Open the attached project
2. Add your cRIO target to the project
3. Copy/Move all the items from the existing RT/FPGA target to the target in step 2.
LabVIEW 2018 or later
LabVIEW FPGA Module
LabVIEW RT Module
Any NI FPGA target
You will need to change IOs in FPGA code and recompile this VI for different Targets.
Example code from the Example Code Exchange in the NI Community is licensed with the MIT license.
thank you for the UART(8N1) Example. I think I get it how it works... 🙂
We want to realize a real UART connection with cRIO9067 and NI9401 for reading data from GPS module. As starting point we used your code and used the Serial Monitor of the Arduino Development Platform, but unfortunately doesn't worked. We tried to delete the code part for sending, to keep only the receiving part of the code, but nothing happened.
Do you have any advice to us? We will appreciate your help!
There is a bug in the code:
Please check on the highlighted part of below image:
Receive side case structure should work when Timeout=False (previously it was running at True value).
Until we update the example. please take a note of it. Thanks
Thanks muhammad.kamran.ayub for reporting the bug. I have fixed this issue in version UART 8N1 Example_V1.02_LV2018.zip.