Example Code

Reconfigurable Scopes Synchronization Based on Stream to Host Example

Products and Environment

This section reflects the products and operating system used to create the example.

To download NI software, including the products shown below, visit ni.com/downloads.


  • PXIe-1095
  • PXIe-5171
  • PXIe-6674T
  • PXIe-8880


  • LabVIEW 2020 SP1

Code and Documents





This example will demonstrate the synchronization capability of multiple reconfigurable scope devices (PXIe-5170/1/2) using the PXIe-6674T timing and synchronization module.

The example is built using the standard Stream to Host sample project, modification to the FPGA target is possible, users can add inline DSP and make use of the general purpose PFI lines that are only accessible from the FPGA on these devices.

The HW setup for this demonstration consists of a PXIe-6674T card in the timing slot of a PXI chassis, and arbitrary number of PXIe-517x cards in the other slots. It is advised to take care of proper thermal management considerations, keep the chassis’ fans on high and leave spacing between the cards.



Figure 1. Hardware Configuration

Figure 2. PXI Express Star Connectivity Diagram

Figure 3. PXIe-6674 clock and trigger routing


After downloading the attached zip, open the LabVIEW project and open Stream to Host (Host).vi in the project tree. Set the devices in the appropriate controls, and setup the proper DStarB trigger lines to each of the PXIe-517x modules in your system. Information regarding trigger routing can be found in the user manual of your PXI chassis.

Configure the channel parameters and timing module routing. Make sure to click Send Trigger after the Ready to Trigger indicator turns on.


Figure 4. Synchronization example soft front panel


To get information about the accuracy of the acquisition, switch to the Time Skew Statistics Statistics tab, to get results from delays of adjacent channels, and further statistical analysis such as chart display and histogram.




 Time skew between devices has been measured using Arbitrary Waveform Generator (PXIe-5422) and RF splitter.

Figure 5. HW Setup for time skew measurement


The connection diagram above describes the architecture of this application. The timing device shares its onboard OCXO clock to the PXI backplane, so each scope can derive their sample clock from the same clock source. The start trigger for the acquisition is also shared from the PXIe-6674T card, using the DStarB trigger lines.

Time skew between devices during run to run is changed  sample=4ns. Standard deviation is up to 1ps.


Figure 6. Device to device time skew, histogram. Mean and std values



Example code from the Example Code Exchange in the NI Community is licensed with the MIT license.