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This example uses the LabVIEW FPGA to implement a phase locked loop, mixer, and low pass filter.
A Lock-in Amplifier is an instrument that can detect the amplitude and phase of sinusoidal signal with known frequency in an extremely low signal to noise environment. This example shows how to use LabVIEW FPGA to build a lock-in amplifier on a CompactRIO. The following diagram illustrates the principle of a Lock-in Amplifier. A Phase Locked Loop (PLL) will lock to the frequency in the reference channel and generate a clean sinusoidal wave. It then multiplies the signal in the mixer, modulating the weak sinusoidal wave in signal channel to DC frequency. After a low pass filter, the amplitude and phase of weak sinusoidal wave can be revealed.
In this example, PLL, mixer and low pass filter are implemented by LabVIEW FPGA. The performance of FPGA based lock-in amplifier can be summarized below:
cRIO 9104 NI 9233
50kHz, limited by 9233
1ms to 20ks
20dB, 40dB, 60dB, 80dB
<-100dB, determined by 9233
For detailed description on the principle of lock-in amplifier, see Principle of Lock in amplifier.pdf in attached file. For detailed description on how to setup the example, including hardware and software requirements, see LIA_IPnet_Readme.pdf in attached file. A simplified version of Lock-in Amplifier is also available on the Xilinx academic SPARTAN 3E XUP Board.
Steps to Implement or Execute Code
Download the relevant code for your LabVIEW version
Retarget for your device or create your own target and move all the VIs and resources to the new target
LIA_FPGA.vi is the top FPGA VI, please move the associated files if you are creating a new target
Compile LIA_FPGA.vi by opening the VI and clicking the run button
Open host.vi under My Computer target
You can control sampling frequency of AD converter, decimation factor of first and second CIC filter, number of stages (1 or 2) and decimation factor of MA filter, or the center frequency of PLL in the GUI
Run the VI and press the Start button
LabVIEW 8.6 "or compatible" (See note at the end of the document)
LabVIEW FPGA 8.6 "or compatible" (See note at the end of the document)
Spartan3E Academic Board
Signal Generator or Other Signal Source
Voltage Offset Circuit for Analaog Input Range
Steps to Implement or Execute Code
1, Please download LIA_IPnet.zip if you are using LabVIEW FPGA 8.6.
2. Please download LIA_IPnet_LabVIEW2009.zip if you are using LabVIEW FPGA 2009.
3. If you are using cRIO DSA modules other than cRIO-9233, you need to change the cRIO module under the FPGA target, update the Data Rate control in FPGA VI and Host VI, and modify the NILIA_9233fs.vi to make the sampling frequency mapping correct for your module.
4. New projects for lock-in amplifier on Xilinx SPARTAN-3E XUP Starter Board are added. Because of fewer resources on SPARTAN-3E FPGA chip, this lock-in amplifier is a lite version, compared with the implementation for cRIO.
Please download LIA_spartan86.zip if you are using the starter board with LabVIEW FPGA 8.6
Please download LIA_spartan2009.zip if you are using the starter board with LabVIEW FPGA 2009
5. New project for lock-in amplifier on sbRIO-9642 is added. The key part of the lock-in amplifier is the same as the one for SPARTAN-3E FPGA chip. The difference is that it uses the I/O nodes offered by NI. The project is a code reference for sbRIO users to get started with the lock-in.
Additional Information or References
**This document has been updated to meet the current required format for the NI Code Exchange. For more details visit this discussion thread**
Example code from the Example Code Exchange in the NI Community is licensed with the MIT license.