The Texas Instruments ADS1258 outputs digitized 24-bit analog voltages in a 4-byte (STATUS Byte plus three data bytes) format through the SPI serial interface accessed via the P5 3.3V Digital I/O Connector on the sbRIO. For more information on the SPI Protocol, please see Understanding the SPI Bus with NI LabVIEW and Implementing SPI Communication Protocol in LabVIEW FPGA. The necessary SPI signals are: SCLK, CS, DRDY, START, MISO (DOUT), and MOSI (DIN). This particular device requires a CPHA and CPOL = 0 and is hard coded onto the FPGA. To select which channels to read and to setup sampling parameters, a command is sent to the device to write the configuration registers after toggling the CS line. Reading data requires that 32-bits of data are clocked to the device with CS tied low in Auto-Scan mode.
This example uses a device specific LabVIEW FPGA implementation of the SPI bus to communicate with an ADS1258 ADC through a TI ECG Analog Front End Evaluation Board. The core SPI engine was taken from the SPI Protocol available on and modified to work specifically with this device. This was performed to maximize performance and the communication rates in synchronizing the DRDY bit, and to enable streaming of SPI data from the FPGA to the LabVIEW Real Time OS. There are two LabVIEW layers in this example: the first layer is a LabVIEW FPGA interface that performs the SPI communication protocol and configures the device while the second layer is a host API that interacts with the FPGA from a host PC. The real-time SBRIO includes Front Panel VI's to interact with the FPGA and to send data to a host PC application.
A NI sbRIO-9631 is used to connect to the SPI lines of an ADS1258 on a TI ECG Evaluation Board Analog Front End. The following wiring diagram was implemented between the sbRIO P5 3.3V Digital I/O Connector and the TI ECG Evaluation Board using the an adapter created with NI Multisim. The layout to this adapter can be reviewed at: NI sbRIO Adapter to the Texas Instruments Electrocardiogram (ECG) Analog Front End Module
The sbRIO Adapter to the Texas Instruments Electrocardiogram (ECG) Analog Front End Module will connect to either a digital sbRIO or a sbRIO which includes analog I/O capabilities. Power is supplied by the designed adapter board, but could also be supplied from the Analog Output pins on the J7 Analog I/O Connector if used.
There are 4 main steps in order to communicate with the ADS1258:
Using the host API created for communicating with the ADS1258 through the LabVIEW FPGA SPI engine makes it easy to retrieve digitized data. With the example provided, the low-level commands have been abstracted so communicating with the device simply involves setting registers parameters.
To run the program, open ADS1258 Host.vi from the ADS1258 Project.lvproj. This interface is the host to the FPGA SPI core and utilizes remote panel communication in order to run the code on the RealTime target while displaying the data on a PC. The program begins by opening a reference to the top-level FPGA VI and then writing the configuration registers with the Configure ADS1258 VI. Before the configurations registers are written, the core SPI engine starts running and utilizes a hard-coded clock mode with CPOL = 0 and CPHA = 0. As soon as this engine receives data to write to the configuration registers, the engine outputs the commands through the SPI protocol directly after toggling CS. The commands that are written are SPI Reset and Multiple Register Write followed by all register values.
Once the user is ready to begin reading data, the Start ADS1258 VI is called in order to start data conversions and is followed by a ADS1258 Read VI that pulls scaled data from the ADC and displays it on the chart from within a timed loop. When the Start ADS1258 VI is called, the device begins clocking out the 32 bits necessary to retrieve a STATUS byte and three bytes of channel data whenever a falling edge on DRDY is detected. The three data bytes are combined and scaled on the FPGA before they are returned to the RealTime host along with the STATUS byte. Here, it should be noted that the sampling rate is controlled by the timed loop in the real time application. Since timed loops give deterministic operation, sampling rates upwards of 500Hz per channel can be achieved with negligible jitter.
When the user is ready to terminate the read operation, the stop button is pressed on the ADS1258 Host VI. This exits the loop and results in ADS1258 Stop being called in order to stop the SPI engine. Finally, the FPGA reference is closed and the program can be exited properly.
Figure 1. ADS1258 Host.vi Front Panel
To move the example to another target, simply create a new LabVIEW FPGA project with the proper I/O lines and copy the ADS1258 Host.vi, ADS1258 SPI.vi, driver VIs, and FIFOs from this example project. Once the FPGA is recompiled and the correct connections are made, no additional configuration is necessary.
Using the LabVIEW FPGA Module, it is possible to communicate with any SPI based ADC, DAC or embedded sensor. The SPI implementation from this example works with the ADS1258 and is written specifically for this device. For other devices where high data rates are necessary, the overall architecture and interface can be used as a template for streaming SPI communication.
Refer to the following documents to learn more about ECG measurements and the application of Graphical System Design using the NI sbRIO with the TI MDXMDKEK1258 Electrocardiogram (ECG) Analog Front End (AFE) module:
Learn how to test and validate any Electrocardiography (ECG) (EKG) based medical device to ANSI/AAMI EC13.
In this document, you will learn how to automate and reduce time required to test and validate any ECG based device using NI PXI modular instruments and NI software.
Example code from the Example Code Exchange in the NI Community is licensed with the MIT license.