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This example demonstrates how to decode digital I²S bus data into audio channels with LabVIEW FPGA.
The example demonstrated how to decode a I²S signal using LabVIEW FPGA. The code can be used on most LabVIEW FPGA targets (e.g. R series, CompactRIO) that support high-speed digital input. I²S is used to encode digital audio data within systems and components. For example digital audio inside of an MP3 player or DVD player is commonly communicated using the I²S protocol.
The example uses a Single Cycle Timed Loop in the FPGA diagram to monitor the three signals of the I²S protocol.
It monitors the LRClk (WS) and SClk lines looking for signal transitions/edges, and collects data bits from the SData (SD) line, writing completed audio samples to a DMA buffer for transfer to the host VI.
LabVIEW Full Development System 2012 (or compatible)
LabVIEW FPGA Module 2012 (or compatible)
LabVIEW Real-Time Module 2012 (or compatible), if you use a RealTime Target for the Host VI
You have to migrate this example to your LabVIEW FPGA Target. You must recompile the FPGA VI.
Steps to Implement or Execute Code
Download and open the attached ZIP-file
Open the [Host] Display I2S Data.vi inside the LabVIEW project and follow the instructions on the Front Panel
Additional Information or References
**The code for this example has been edited to meet the new Community Example Style Guidelines. The edited copy is marked with the text ‘NIVerified’. Read here for more information about the new Example Guidelines and Community Platform.**