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This example demonstrates how to include VHDL code in LabVIEW FPGA with the HDL Interface Node.
This example demonstrates how to import the functionality of IP in a .vhd file into LV FPGA using the HDL node. It replicates a simple and function that is coded in VHDL and imported into LV using an HDL Node.
LabVIEW Full Development System 2012 (or compatible)
LabVIEW FPGA Module 2012 (or compatible)
No hardware is necessary to use this example VI
Steps to Implement or Execute Code
Download and open the attached ZIP-file
Open the VI and follow the instructions on the Front Panel
Additional Information or References
Note: Keep in mind that the HDL Interface Node was replaced with the IP Integration Node in LabVIEW 2010. The HDL Interface Node should only be used if you must use LabVIEW 2010 or earlier or if you already use it in an existing application.
**The code for this example has been edited to meet the new Community Example Style Guidelines. The edited copy is marked with the text ‘NIVerified’. Read here for more information about the new Example Guidelines and Community Platform.**