HIL Automotive Engine Simulation Reference Example

[ExamplePrograms]

Description

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Overview

This example and web content has not been updated for use with the Automotive Engine Simulation Library 2.0 or later. Much of the content is the same, however, there are some differences.

This reference example demonstrates how to simulate and output cam and crank signals of an engine for testing ECUs. It also demonstrates how to capture crank related signals such as fuel injection and ignition coil signals from an ECU. This application can be used as an out-of-the-box simulator to plug in with the Veristand HIL environment or used as a reference to create a customized Engine Simulation.

Instructions

1. Download the reference application: engine_simulation_2009.zip
2. Unzip the files to a working directory. Two folders are extracted to the working directory, AES which contains the Automotive Engine Simulation (AES) Library , and Engine Simulation 2009 which contains the project for this example.
3. Browse to Device Connections directory and open images to display I/O connections.
4. Browse to the Engine Simulation 2009 directory and open Engine Simulation.lvproj
5. Within the project explorer, open Engine Simulation - RT Host.vi found under the PXI RT target.
6. Open the Block Diagram, and configure the Open FPGA VI Reference to open the reference for either the 7833R or 7842R.
7. Run Engine Simulation - RT Host.vi, make configurations on the Configurations page, and click the Start button.

View the parts list for this system now!

Engine Simulation Overview

This example simulates cam and crank engine signals as well as knock sensor, generic analog output, PWM output, and throttle body motor control output. In addition to simulating engine outputs, this example also acquires fuel injector and ignition coil signals which are related to the simulated crank angle.

The signal generated by a particular cam or crank varies depending on the tooth configuration on the sensor in question. This example allows for the configuration of a crank that is defined by a certain number of teeth with a certain number of teeth missing. It also allows for the configuration of multiple cams that are defined by an array of values that define the angle in degrees at which each rising edge and falling edge of a tooth occurs. RPM is adjusted during run time. Additionally, the crank angle is monitored and used to synchronize the rest of the data.

Cam VVT functionality is included by providing cam offsets that are adjusted during run time. The cams can also be set to rotate at half the speed of the crank for four-stroke cycle simulation. The knock sensor is synchronized to the crank and can be run periodically at a specific crank angle.  The user configures the period and the frequency.  

Fuel injection and ignition coil signals are captured and angle related measurements are made.  By measuring the start and end angles based off the crank angle, the code determines the duration of the signal.  Additionally, there is a variety of digital and analog IO available for use.

Crank Generation

Crank generation consists of an angle processing unit which runs on the FPGA, the loop that the angle processing unit is running in, and the Real-Time connectivity which is responsible for configuring the FPGA loop and updating RPM.

Crank Angle Processing Unit

The crank angle processing unit is provided by AES Crank APU with Output.vi found in the Automotive Engine Simulation (AES) Library. It features high-speed crank generation up to 208,333 RPM with resolution of.00000001 RPM. It also features .00015 degrees of angular resolution at 1,000 RPM, .0015 degrees of resolution at 10,000 RPM, and .015 degrees of resolution at 100,000 RPM for precise crank digital output updates and precise relationships of crank related acquisitions such as fuel injection and ignition coil sparks. Note that resolution changes linearly with respect to RPM.

FPGA Crank Generation Loop

The crank generation loop simulates a crank of the type specified by a certain number of teeth with a certain number missing (i.e. 60 teeth; 2 missing). Where the missing teeth occur with respect to Top-dead-center is configured by the Missing Teeth Offset input. The duty cycle of a tooth with respect to its gap is configured by specifying different number of Degrees High Pulse for the tooth and number of Degrees Low Pulse for the gap. Top-dead-center is specified as occurring on a tooth or a gap by setting the Top-Dead-Center High or Low input. These configurations should be made before the FPGA is run and should not change thereafter.

The crank generation loop implements the AES Crank APU with Output.vi. It allows the flexibility to configure the Degrees High Pulse and Low Pulse, Number of Teeth Missing, Missing Teeth Offset from Top-Dead-Center, and Top-Dead-Center High or Low. The configurations are designed to be set by the Real-Time host prior to running the FPGA VI. The Degrees per Tick is generated by the RPM and can be dynamically changed during execution. This loop then provides the Crank Angle to the rest of the system for crank related measurements and toggles a Crank Digital Output. 

The crank signal is output on both a 3.3V line on the R Series connector and a line on the 9474 module. The 9474 can source up to 30V specified by the Vsup. See details of the 9474 for more information.

Figure 1: Crank Generation FPGA Loop

Real-Time Host Connectivity

The Real-Time host connectivity consists of the configuration for the crank made before the FPGA runs and the continued update of RPM that the engine runs at.

Configuration

The user configures the simulated crank type by specifying the Number of Crank Teeth, Duty Cycle of Tooth/Gap, Number of Crank Teeth Missing, Missing Teeth Offset, and the whether Top-Dead-Center is High or Low. The AES Library's AES Crank Degrees per Tooth.vi is used to calculate the Degrees High Pulse and Degrees Low Pulse for the crank teeth and gaps from the user specified Number of Crank Teeth and Duty Cycle.

The screenshot below demonstrates the crank configuration portion of this example. It does not fully represent the code included in this example since the other configuration components have been removed. It does demonstrate how the configurations are made. As seen below, once the Real-Time application is run, changes can be made to the configurations. Once the configurations have been set, the user clicks the Start button. At that point, the crank configuration is loaded to the FPGA and then told to run. Please note that the Open FPGA VI Reference should configured not to Run the FPGA VI.

Figure 2: Crank Real-Time Configuration

RPM Updates

The screenshot below demonstrates the RPM update portion of this example. The AES Library's AES Crank Degrees per Tick.vi is used to convert from a user requested RPM to degrees of rotation per FPGA tick that is used by the FPGA Crank Generation Loop. In a completed application, the requested RPM would normally come from a model running on the Real-Time system.

Figure 3: Real-Time Update Engine RPM

Cam Generation

The cam generation is coupled to the angle produced by the crank's angle processing unit. A user specifies the angles for both the rising and falling edges of the cam output. When the crank's angle reaches one of the angle values specified in the cam's configuration, the cam output updates.

Cam Features

The cam functionality is provided by AES Library's AES Cam VVT with Output.vi. It features a fully configurable cam tooth profile by using an array of values to specify the rising and falling edges of each cam tooth. This implementation allows for up to 32 teeth of varying widths to be configured for each cam. The angles must be provided in order from lowest to highest. The first angle provided can also be configured as a rising edge or falling edge.

The cam can either run at the same speed as the crank or at half the speed of the crank. This functionality allows the user to configure cams for either two-stroke or four-stroke cycles. The cam also features variable valve timing (VVT) functionality by allowing the user to adjust an offset to the cam profile during run-time.

FPGA Multiple Cam Loop

This example features a multiple cam loop running on the FPGA which implements up to four cams with VVT functionality. The cam tooth configuration is loaded by setting the Cam Number of Angles and Cam Number of Cams and transferring the angles from Real-Time host via DMA FIFO. The designation of whether the first angle is a tooth or gap is configured by the Cam First Rising input. It also allows the flexibility to run the cam at half the speed of the crank by setting the Cam Half Speed input. These configurations should be set by a Real-Time host prior to running the FPGA VI.

The loop will continue to read cam angles from a DMA FIFO as long as the number of angles previously read is less than the number of angles specified in the Cam Number of Angles control multiplied by the number of cams specified in the Cam Number of Cams control. When reading angles from the DMA FIFO, the AES Cam VVT with Output.vi is executed with an input Write Cam Angle when the angle corresponds to its particular cam. Cam angles will be loaded into the configured number of cams in an interleaved fashion. Once the total number of angles are read from DMA FIFO and written to the AES Cam VVT with Output.vis, the loop then continually executes with an inputs of Update Cam Output to the cam VIs. On the first rotation of the cam, the cam output will not be updated until all of the cam angles are read from the DMA FIFO. This delay should equal the number of cam angles multiplied by the number of cams multiplied by the FPGA clock period because the angles were written to the DMA FIFO and transferred prior to running the FPGA.

The Crank Adjusted Angle output is simply the crank angle if the cam is not running at half speed (two-stroke cycle). If the cam is running at half the speed of the crank (four-stroke cycle), the Crank Adjusted Angle is the crank angle from 0 - 720 degrees instead of 0 - 360 degrees. This adjusted angle can then be used by any crank related signal acquisition.

The cam signals are output on both a 3.3V line on the R-Series connector and a line on the 9474 module. The 9474 can source up to 30V specified by the Vsup. See details of the 9474 for more information.

Figure 4: Cam Generation FPGA Loop

Real-Time Host Connectivity

The Real-Time host connectivity consists of the configuration for the cams made before the FPGA runs and the continued update of the cam profile offsets used to implement VVT.

Configuration

The user configures the four simulated cams by providing a 2-D array of values in the Degree Offsets control which specifies the rising and falling edges of each cam tooth for each cam. This implementation allows for up to 32 teeth of varying widths to be configured for each cam. The angles must be provided in order from lowest to highest. The first angle provided can also be configured as a rising edge or falling edge by setting the Cam First Angle Rising input.

The screenshot below demonstrates the cam configuration portion of this example. It does not fully represent the code included in this example since the other configuration components have been removed. It does demonstrate how the configurations are made. As seen below, once the Real-Time application is run, changes can be made to the configurations. Once the configurations have been set, the user clicks the Start button. At that point, the cam configuration is loaded to the FPGA and DMA FIFO. Then the FPGA is set to run. Please note that the Open FPGA VI Reference should configured not to Run the FPGA VI.

The Degree Offsets is checked to make sure that an even number of angles are entered for each cam. If not, the last angle is cut off. An even number of angles must be provided since each tooth must have a rising and a falling edge. The number of angles and number of cams are set on the FPGA, and each angle is converted from floating point to fixed point and then loaded into the DMA FIFO.

Figure 5: Cam Real-Time Configuration

VVT Adjustments

The screenshot below demonstrates the cam VVT update portion of this example. In a completed application, the requested VVT offsets would normally come from a model running on the Real-Time system.

Figure 6: Real-Time Update Cam VVTs

Crank Related Signal Acquisition

In order to fully test an ECU with an HIL engine simulation, the engine simulator must be able to acquire the fuel injection and ignition coil signals sent from the ECU. In most cases, the time duration of the fuel injection and the crank angle when the ignition coil signal goes high is required. For flexibility, this example latches the crank angle at rising edge, crank angle at falling edge, angle duration, and time duration of the fuel injector and ignition coil pulses by utilizing AES Library's AES FI IC Pulse Capture.vi.

The ECU may output the fuel injectors and ignition coil signals at either 5V or batter level voltage. For this reason, this example allows the user to specify the voltage level for both the fuel injectors and the ignition coils. If 5V is selected, the signals are acquired on the R Series connector. If 12V is selected, the signals are acquired on the 9426 module in the R Series Expansion Chassis. Please note that the signals on the 9426 are not necessarily 12V, but are at the voltage level (up to 24V) specified by the Vsup on the 9426 module. See details of the 9426 module for more information.

Figure 7: Fuel Injector Pulse Capture FPGA Loop

PWM Generation and Acquisition

Engine Simulation HIL systems may require a variety of PWM Inputs and Outputs. This reference example includes PWM Generation and Acquisition on the FPGA and conversions to/from frequency and duty cycle on the Real-Time host.

FPGA Loops

Four PWM inputs and four PWM outputs are included on the TTL compatible R-Series connector. Four PWM inputs are acquired on the 9426 module at voltage values specified by Vsup, and three PWM outputs are generated on the 9474 module at voltage values specified by Vsup.

PWM Input

The screenshot below demonstrates the PWM acquisition on the FPGA. The high time and low time for each PWM signal is recorded so that the Real-Time host can read it and calculate frequency and duty cycle.

Figure 8: PWM Input FPGA Loop

PWM Output

The screenshot below demonstrates the PWM generation on the FPGA. The high time and low time for each PWM signal is provided by the Real-Time host, and the FPGA generates the four 3.3V PWM outputs and three PWM outputs at the Vsup level on the 9474 module.

Figure 9: PWM Output FPGA Loop

Real-Time Calculations

The Real-Time host gives connectivity to the PWM acquisition and generation on the FPGA and is responsible for conversion to/from frequency and duty cycle.

PWM Input

The low time and high time in terms of FPGA clock ticks of the PWM inputs are read from the FPGA. These values are then converted to Frequency and Duty Cycle as shown in the image below.

Figure 10: Real-Time PWM Input Calculation

PWM Output

The user specifies frequency and duty cycle on the Real-Time host. These values are then converted to Low Time and High Time in terms of FPGA ticks in order to generate the PWM outputs on the FPGA.

Figure 11: Real-Time PWM Output Calculation

Throttle Body Control

An example of a throttle body control loop is included on the FPGA. The lower loop displays the feedback and PID that produces the PWM output that is sent to the output loop. The output loop then drives the servo motor output from a PWM signal.

In a user's final application, the setpoint for the feedback loop can be specified by a model or by a PWM input.

Figure 12: Throttle Body Control Loop

Knock Sensor Generation

An example knock sensor simulation is included. From the Real-Time host, the user specifies the crank angle in which the knocking begins, the duration of the knocking, the frequency of the knocking, and the amplitude of the knocking. The FPGA then waits until the crank angle is between the knock sensor start angle and the knock sensor start angle plus an additional crank tooth. Once this angle is reached, a sinusoidal output is generated for the duration specified and at the amplitude and frequency specified. The amplitude of the knocking output does not decrease with time, and once the duration has ended, the output is updated with 0 V.

Figure 13: Knock Sensor Loop

Additional Resources

For an out-of-the-box simulator by using this FPGA personality with the Veristand HIL environment, please the VeriStand Add-ons page. 

Feedback

This reference application was created by the NI AE Specialists group.

We do not regularly monitor Reader Comments posted on this page.

Please submit your feedback in the Automotive Engine Simulation Discussion Forum so that we can improve this component for future applications.

Please direct support questions to NI Technical Support.

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