Overview
This example demonstrates the use of pipelining in LabVIEW FPGA and illustrates a comparison of clock cycles between a standard loop and a loop implementing pipelining techniques.
Description
This project uses a CompactRIO with an analog input module and an analog output module. It contains two separate FPGA VIs. One VI uses standard practices while the other incorporates pipelining techniques. They both read from four analog channels, perform a random scaling operation, and output to four analog channels with a benchmarking clock running in parallel. Each individual VI should be run separately and interactively to observe the differences in the number of clock cycles it takes to run each program.
The program can be modified for any FPGA hardware but results may vary.
Requirements
Software
LabVIEW 2013 (or later)
LabVIEW FPGA Module 2013 (or later)
NI-RIO 13.0 (or later)
Hardware
cRIO-9014 (cRIO controller)
cRIO-9113 (cRIO chassis/FPGA)
NI 9201 (analog input module)
NI 9263 (analog output module)
Steps to Implement or Execute Code
Additional Images or Video
**This document has been updated to meet the current required format for the NI Code Exchange.**
Example code from the Example Code Exchange in the NI Community is licensed with the MIT license.