Example Code

FPGA Configuration file to use myRIO with VeriStand

Products and Environment

This section reflects the products and operating system used to create the example.

To download NI software, including the products shown below, visit ni.com/downloads.


  • myRIO-1900
  • myRIO-1950


  • LabVIEW
  • LabVIEW FPGA Module
  • LabVIEW Real-Time Module
  • Veristand

Code and Documents



This document shows how to use the FPGA I/O of a myRIO-1900 or 1950 with NI VeriStand. However, I think that it could also apply to any cRIO device.


If you are only interested to use a myRIO with VeriStand 2017, you can simply use the FPGA bit (myRIO-1900_HaroTekDemo001.lvbitx) and configuration (myRIO-1900_HaroTekDemo001.fpgaconfig) files attached as a zipped file to this document (myRIO-FPGA_Config_Bit_Files.zip). Simply copy those two files to C:\Users\Public\Documents\National Instruments\NI VeriStand 2017\FPGA and then select “myRIO-1900_HaroTekDemo001.fpgaconfig” for the FPGA configuration file. This configuration give access to the AI and AO channels of Connectors A and C, to digital input on DIO 0 to 3 on Connector C, to digital output on DIO 4 to 7 on Connector C, and to LED 0 to 3.


The topics covered in this document are also addressed in the video below. The video also includes a demonstration on how to use the configuration file in VeriStand.


The steps on how to create FPGA personalities for VeriStand are described in the two documents linked below. However, I still struggled through the different steps to achieve that goal so I thought I would create an additional more detailed document that would complement these two documents:


NI VeriStand FPGA-Based I/O Interface Tools: forums.ni.com/t5/NI-Labs-Toolkits/NI-VeriStand-FPGA-Based-I-O-Interface-Tools/ta-p/3493285 .

Creating FPGA-Based I/O Personalities for NI VeriStand: www.ni.com/en-us/innovations/white-papers/09/creating-fpga-based-i-o-personalities-for-ni-veristand.... .


There are two main steps to be able to use the I/O of a myRIO with VeriStand:


  1. Creating the FPGA VI that actually controls the I/O from VeriStand
  2. Creating the FPGA configuration file (*.fpgaconfig) required by VeriStand to know how the user can access the myRIO I/O.

These two steps are described in the section “How to Use”. The LabVIEW project, FPGA VI, and, associated FPGA configuration files for VeriStand are provided in a zipped file (myRIO FPGA Project - LV2017.zip) attached to this document. Those files are compatible with LabVIEW 2017 SP1 and VeriStand 2017.

This document is a complement to the document NI VeriStand FPGA-Based I/O Interface Tools: forums.ni.com/t5/NI-Labs-Toolkits/NI-VeriStand-FPGA-Based-I-O-Interface-Tools/ta-p/3493285

which contains the link to Creating FPGA-Based I/O Personalities for NI VeriStand: www.ni.com/en-us/innovations/white-papers/09/creating-fpga-based-i-o-personalities-for-ni-veristand.... .

LabVIEW Model on myRIO with VeriStand

As long as you have installed the proper drivers (more on this in the “How to Use” section), it is pretty straight forward to create a model using LabVIEW and to upload it onto the myRIO within VeriStand. This part is not going to be covered in this document. The only difficulty is that you need to create a VeriStand model for the myRIO using LabVIEW compatible with VeriStand, you also need to have:


VeriStand LabVIEW Models for NI Linux Real-Time Targets: www.ni.com/en-us/support/downloads/software-products/download.veristand-labview-models-for-ni-linux-...

How to Use

Driver Installation

This section is very important. It is the part of the process that took me the most time to get right. I am hopefully covering everything I did but I cannot guarantee that I did not forget one or more steps.

Windows Host

In a first step, you have to make sure that the proper drivers are installed on your Windows PC.

After installing LabVIEW, you need to install the corresponding VeriStand version. As far as I can tell, the LabVIEW and VeriStand versions must match. Your LabVIEW version must include the RT and FPGA modules.


When specifically using a myRIO, it is useful (if not essential) to have the LabVIEW myRIO toolkit: https://www.ni.com/en-us/support/downloads/software-products/download.labview-myrio-toolkit.html#305...


When installing VeriStand, make sure that you include LabVIEW support for VeriStand: https://knowledge.ni.com/KnowledgeArticleDetails?id=kA00Z000000fzLbSAI&l=en-US

To make the development of the FPGA VI easier, you should download and install the NI VeriStand FPGA Interface Tools (attachment to “NI VeriStand FPGA-Based I/O Interface Tools” referred to earlier)  : https://forums.ni.com/ni/attachments/ni/7324/12/1/NI%20VeriStand%20FPGA%20Interface%20Tools%202010+%.... This step is necessary only if you want to start from scratch. If you use the files attached with this document, you can skip this step (and possibly the following one).

When it will be time to generate a template FPGA VI for VeriStand, there are no template for the myRIO. You have to start from one of the templates for a cRIO. To access these templates, you need to install the CompactRIO driver: https://www.ni.com/en-us/support/downloads/drivers/download.ni-compactrio.html.


It is important to also install the appropriate drivers on your myRIO. I would recommend that you go to NI MAX and format the myRIO. Then, select the software header and click “Add/Remove Software”


Based on the software that you currently have on your Windows PC, I highly recommend that you select the Software Stack proposed by NI MAX. Select the one that matches the LabVIEW and VeriStand version that you intend to use. Notice that in my case, I could use the “LabVIEW Real-Time 17.0.0” to upload and run a LabVIEW model but I could not make the FPGA I/O work. I had to select “LabVIEW 17.0.2” for both model and I/O to work (see Figure 1).


Figure 1 List of software stacks available to install on a myRIO from NI MAX. The list depends on the applications installed on the Windows PC. Select the one that corresponds to your LabVIEW and VeriStand version.


Once the software stack has been installed, go back to the “Add/Remove Software” and select “Custom software installation (currently installed)”, as shown in Figure 1.

Scroll down to “NI VeriStand Engine XXXX”. Click on it and select the version that you want to install (see Figure 2). NI MAX is going to automatically select other drivers that need to be installed along the engine. Do not change any of those selection. Complete the installation.


Figure 2 Installation of the NI VeriStand Engine. Make sure to select the version matching the version of VeriStand and LabVIEW that you intend to use.


Notice that you cannot run a VI onto the myRIO from LabVIEW and then use the same myRIO with VeriStand. VeriStand is not going to work anymore with the myRIO after running a VI from LabVIEW. You need to use NI MAX to remove the VeriStand engine from the myRIO, and then reinstall it for VeriStand to work with the myRIO again (https://forums.ni.com/t5/NI-VeriStand/VeriStand-error/m-p/2148674#M1939).

FPGA VI Template

This section describes how to create the FPGA VI from scratch. If you simply intend to use the attached LabVIEW project files, you can skip to section 3.3 FPGA VI.

Follow the steps describe in the document referred earlier in this document “NI VeriStand FPGA-Based I/O Interface Tools” (https://forums.ni.com/t5/NI-Labs-Toolkits/NI-VeriStand-FPGA-Based-I-O-Interface-Tools/ta-p/3493285).


  1. Create a new project using the “NI VeriStand FPGA Project” template.
  2. In System Setup, select “Create new system”. There is no setup available for myRIO so discovering existing system is not a viable option.
  1. Select CompactRIO Reconfigurable Embedded System (https://forums.ni.com/t5/Academic-Hardware-Products-myDAQ/myRIO-and-Veristand/m-p/4019294#M7289).
  1. Select a controller, a chassis, and a module.

The trick is to make sure that the Compact RIO driver had been installed. If not, no controller, no chassis, and no module will be available to select. The list of controllers shown in Figure 3 would then be empty.


Figure 3 List of Compact RIO Reconfigurable Embedded System available to create a LabVIEW project template. If the Compact RIO driver had not been installed on the Windows PC, this list would be empty.


To generate the files attached with this document, I selected:

  1. 9022 controller
  2. 9101 chassis
  3. 9381 module (I selected the 9381 because it contains AO, AI, and DIO, like a myRIO).
  1. Give a name to the project and a location to save it.
  1. Open the project (see Figure 4).


Figure 4 Project as created from template before any modification to fit a myRIO.


  1. Add a myRIO target. You might have to enter the IP address your myRIO.
  2. Move the “9381 FPGA VeriStand project FPGA.vi”, “cRIO-9101 9381 FPGA VeriStand project.fpgaconfig”, DMA_WRITE, and DMA_READ items from “FPGA Target (RIO0, cRIO-9101)” to “FPGA Target 2 (RIO0, myRIO-1900)”.
  3. Remove “RT CompactRIO Target ( from project. Your project should then look like Figure 5.

Figure 5 LabVIEW project after adding myRIO target, moving the FPGA VI, FPGA configuration file, DMA_WRITE and DMA_READ; and removing the Compact RIO target from the project.


  1. Open 9381 FPGA VeriStand project FPGA.vi


  1. In my case, I deleted the PWM parallel loops and the corresponding controls (in red in Figure 6). I deleted the PWM parallel loops because this is not a feature that I intended to use with the myRIO. If you want to use PWM with your myRIO, just keeps those loops and adjust the I/O references accordingly.


Figure 6 Deleting the parallel loops for PWM control (within the red border in figure above).


  1. In the remaining main loop, change the FPGA I/O references to match the FPGA I/O of the myRIO. In my case, I selected the DIO of connector C (DIO 0 to 3 as input, and DIO 4 to 7 as output), and the AIs and AOs of Connector C and A. I also added LED 0 to 3 as DIO output.
  1. Remove broken wires and remove unused build array inputs and unused index array outputs. Make sure that the run arrow VI is not broken anymore. The VI is not ready yet to be compiled. The necessary edits are described in section 3 FPGA VI.


As mentioned in the previous section, you can just change each reference of the I/O in the template VI by a I/O reference of the myRIO. Just click on the triangle at the right of the reference and select the I/O you want to use, as shown for the Input DIO in Figure 7.


Figure 7 Selecting a I/O reference from a myRIO device.


Just changing the I/O references is simple and should work as long the I/O you change have the same bit formatting. DIOs should not be an issue since each I/O correspond to a single bit. In the case of AI or AO, there might be a difference in the number of bits that might need to be addressed. Also, there is the PWM inputs and outputs, if they have been deleted. If you did not deleted them, you can simply replace each reference by the corresponding PWM reference on the myRIO. I have not tested it though.


The communication between VeriStand and the FPGA board is done through DMA. I/O Data are interleaved. Data is transferred through the DMA FIFO by packets. The data type of the packet is configurable. In the present case, it is set to U64.


For communication from the FPGA board to VeriStand, a U64 array is wired to a For Loop that contains the “NI VeriStand – Send Packet to Host.vi”. Each element of that array contains some of the data. The first element is required for timing and should be left as-is. The second element contains the digital inputs from the FPGA board. In my case, I wanted to change the number of DIO outputs. So I deleted the subVI “4 Ch Digital Input.vi” and the cluster of I/O reference wired to it. I added a I/O FPGA node. I selected “ConnectorC/DIO0” and configured it for Read. I added 3 more nodes by dragging the bottom of the I/O node to get the ConnectorC/DIO 1 to 3. Each output of the node is a bit. Building an array of Booleans from those outputs and using the “Boolean Array to Number” function, I get a U8 number of which the first four bits represent the values of those four digital inputs. The U8 number is then combined into a U16 with a value of 0, the resulting U32 is then combined with a value of 0 to form a U64. That is the second packet. Notice that this packet of 64 bits contain only 4 bits of useful information. More digital inputs could easily be added. Also notice that the number containing the useful information is always added to the lo input of the “Join Numbers” function. The result is that the four bits are the first four bits of the U64 packet. Also notice that the code to convert the digital inputs into a U64 can be copied from the subVI “4 Ch Digital Input.vi”.


A similar approach is used for the Analog inputs. The cluster and subVI are deleted and a FPGA I/O node is added. The ConnectorA/AI0 and AI1, and ConnectorC/AI0 and AI1 are added. Each output of the node is 16 bit (the AI on myRIO is 12-bit but coded on 16-bit, the last 4 bits are not used). Combining the four outputs together requires 64 bits which makes the third packet. Notice that as for the DIO, the lo inputs of the “Join Numbers” function correspond to the lower bits of the U64. It means the analog input data will arrive to VeriStand in the order from bottom to top. This is important when modifying the FPGA configuration file.


Data is sent from the FPGA board to VeriStand, one U64 packet at a time using the subVI “NI VeriStand – Sent Packet to Host.vi”. Data is received one U64 packet at a time by the FPGA board from the Host by the “NI VeriStand – Receive Packet from Host.vi”.


The For Loop should be configured to run for the expected number of packets. The output of the For Loop is an array of U64, each element representing a packet. In the present case, the first packet is used for the digital data. I deleted the cluster and the subVI and I added a FPGA I/O node configured for 8 digital outputs (configured for Write). The first packet is converted into an array of Booleans and the first 8 elements are wired to the 8 digital outputs of the I/O node.

The second U64 packet is broken down in four 16-bit values that are written to a I/O node containing ConnectorC/AO 0 and 1, and ConnectorA/AO 0 and 1. Notice that the U16 values are explicitly converted to I16 for ConnectorC/AOs to avoid coercion dots because those AOs can output +/- 10V and would therefore accept negative values. ConnectorA AOs only output 0 to 5 V.


The resulting FPGA VI block diagram is shown in Figure 8.


Figure 8 Final block diagram of the FPGA VI after modifications.


The FPGA VI can then be compiled into a FPGA bit file.

FPGA Configuration File

The information on how the data is transferred back and forth between VeriStand and the FPGA device within the VI is provided to VeriStand by the FPGA Configuration file.

The FPGA configuration file uses an XML format.


Figure 9 below shows the top of the default FPGA configuration file for VeriStand created by the VeriStand FPGA project template.


Figure 9 Default FPGA configuration file created along with the VeriStand FPGA Project Template.


The first modification of the configuration file is the name of the bit file, as compiled from the FPGA VI created in the project. In the example of Figure 9, “cRIO-9101 myRIO Project.lvbitx” should be replaced by the name of the file used when compiling the FPGA VI.


The second modification would be within <Categories>. The Categories are how the FPGA I/O connections are being grouped within VeriStand. The first Category is <Input>, as shown in Figure 10. Sub-categories are Analog and PWM. You can change those sub-categories and descriptions as desired. The modifications will show up in VeriStand when it is time to use the FPGA I/O. A Category <Output> after <Input> with similar sub-categories can be modified similarly.


Figure 10 Input Category of the default FPGA configuration file.


The following sections are for the data themselves. A first section is <DMA_Read>. This section describes how the data are packaged into the packets.


Figure 11 <DMA_Read> section of the default configuration file.


The total number of packets per dataset is given by <Packets>6</Packets>. The default configuration file has six packets but this number should be changed for the actual number of packets used in the FPGA VI. In the present case, the modified number of packets is three.


The first packet from the FPGA inputs to VeriStand is for timing and should be left as-is. The second packet is for digital inputs. In the default file, digital inputs are packet per port, using a single U8 for the four digital channels.


For the modified configuration file, shown in Figure 12, the digital inputs can also be packed per line, using four sub-sections, with four <Boolean> … </Boolean> instead of a single <U8>…</U8>. A name and description can then be given to each individual line, as. Notice that going from a configuration per port to a configuration per line only has an impact within VeriStand. Therefore, two configuration files can be created, one using digital ports and the other one using digital lines, for the same FPGA bit file.

The order in which the data is packed within a packet is defined within the FPGA VI. When using the “build array” or “index array” functions, the early indices refer to the first bits within a packet. When using the “join numbers” or “split number” functions, the lo part refers to the first bits within a packet. The order within the FPGA configuration must match the order of reading or writing within the FPGA VI.


Figure 12 Configuration of the second packet for digital inputs defined per line using <Boolean>…</Booelan>  in the final FPGA configuration file instead of per port as given in the default FPGA configuration file.


The final configuration of the third packet is shown in Figure 13. Each analog input is provided as a raw 16-bit integer, signed for connector C (+/- 10V), and unsigned for connector A (0-5V).


Figure 13  Configuration of the third input packet in the final FPGA configuration file. The four analog inputs are configured as <I16> or as <U16>.


The following section is for the FPGA outputs, as shown in Figure 14. The configuration of the digital and analog outputs is similar to the one used for the inputs. In the case of the outputs, there are only two packets.


Figure 14 Configuration of the packets for the FPGA outputs in the final FPGA configuration file.


The FPGA configuration and bit files should be copied in the FPGA directory of the public folder of your version of VeriStand. For VeriStand 2017, that directory is: C:\Users\Public\Documents\National Instruments\NI VeriStand 2017\FPGA.


When it is time to configure the FPGA I/O, select the configuration file (*.fpgaconfig) that was created for the myRIO. The list of inputs and outputs should now be available as channels within VeriStand the way it was configured in the configuration file.

Related Links

NI VeriStand FPGA-Based I/O Interface Tools: forums.ni.com/ni/attachments/ni/7324/12/1/NI%20VeriStand%20FPGA%20Interface%20Tools%202010+%201.3.0....


LabVIEW myRIO toolkit: www.ni.com/en-us/support/downloads/software-products/download.labview-myrio-toolkit.html#305910


CompactRIO driver: www.ni.com/en-us/support/downloads/drivers/download.ni-compactrio.html

Marc Dubois
HaroTek LLC

Example code from the Example Code Exchange in the NI Community is licensed with the MIT license.