This example demonstrates how to build a pattern in the Digital Pattern Editor for Source Synchronous Acquisition with a Digital Pattern Instrument.
By using the match opcode and a slightly faster Time Set, the Digital Pattern Instrument can be aligned with an external clock from the DUT. The first thing that must be done is flushing the compare pipeline. In this example the tset_search Time Set is 1/80 less then the normal timing period, this can be seen by looking at the SourceSyncAcq.digitiming sheet. Therefore, the pattern must repeat the first match 80 times to flush the buffer since there is an 80 cycle pipeline delay for the match opcode. Next the tset_search Time Set is used to sweep through the incoming clock to find the falling edge of the clock. This is done by calling jump_if(matched, FindFallingEdge), match and having the Clock pin set to L. This will cause the pattern to loop on this vector until the first falling edge of the clock signal is seen. After the falling edge is found the pattern sweeps through the clock signal to find the rising edge of the clock. The Time Set and Clock pin state is not changed for the next vector. However, jump_if(!matched, FindRisingEdge), match is used to loop on the vector until the first rising edge of the clock signal is seen. The pattern is now aligned with the input clock signal.
Next, the pattern flushes the compare pipeline before looking for DataRdy. Then jump_if(!matched, FindDataRdy), match is called to have the vector loop until the DataRdy pin goes high. The compare pipeline must be flushed to center the pattern on the incoming clock signal after the cycle that DataRdy asserts on is found. This is done by calling a repeat on the normal Time Set R times. Where R = ((Data Word Length*N)-82). After the pattern has been aligned and Data Rdy has been asserted, the data can be acquired using a flat pattern, SourceSyncAcq.digipat, or a capture waveform, SourceSyncAcq_wfms.digipat. Finally, a halt is called to end the pattern.
PXIe Chassis (2x)
VHDCI Cable (SHC68-C68-D4 or SH68-68-D1)
NI-Digital Pattern Driver and Digital Pattern Editor 16.0 or newer
LabVIEW 2014 SP1 (64 Bit) or newer
1. Install all of the above required software.
2. Download and unzip the attached SourceSyncAcq.zip folder.
3. Place one PXIe-6570 in each PXIe chassis and connect the two PXIe-6570s with the VHDCI cable. One PXIe-6570 will be used to acquire the data and the other PXIe-6570 will act as a source. The PXIe-6570s need to be in different chassis so they are running on different clocks.
4. Open the SourceSyncAcqSource DPE project in the SourceSim folder.
5. Open the OneSite.pinmap and match the instrument name with the name of the source PXIe-6570 in NI MAX.
6. Open the RunSource.VI in the SourceSim folder.
7. In the 6570 Resource Name control select the source PXIe-6570.
8. Select OneSite.pinmap for the Pin Map file, SourceSyncAcqSource.specs for the Specifications file, PinLevels.digilevels for the Levels file, SourceSyncAcqSource.digitiming for the Timings file, and SourceSyncAcqSource.digipat for the Pattern file. All of these files are located in the SourceSim folder.
9. Open the SourceSyncAcq DPE project and connect to the acquisition PXIe-6570.
10. Open the OneSite.pinmap and match the instrument name with the name of the acquisition PXIe-6570 in NI MAX.
11. Open the SourceSyncAcq pattern and burst the pattern. Then run the RunSource.VI. To compare the data using a capture waveform burst the SourceSyncAcq_wfms pattern.
Product Support Engineer: Digital Instruments/STS
Example code from the Example Code Exchange in the NI Community is licensed with the MIT license.