PXI and PCI synchronization are very similar in the sense that they use the same reference clock principle. In a PXI system, a common 10 MHz reference clock for synchronization of multiple modules is already built into the backplane with the PXI_CLK10 signal. To synchronize multiple M Series modules in a PXI system, each one of the M Series modules should use the PXI_CLK10 as its reference clock, which will cause the timebases on all boards to be synchronized with one another. If one master device sends out a start trigger to the other devices and all of their sample clocks are set to the same rate, the acquisitions will be synchronized. Figure 1 shows the block diagram representing M Series PXI synchronization.
Figure 1 PXI Synchronization with PXI_CLK10
In Step 1, virtual channels are created. Each of the virtual channels is used to acquire from an analog voltage signal. Notice that they are from independent devices – M Series Master and M Series Slave.
In this step, the timing information is entered. Both channels are set for finite acquisition of 1000 samples/channel at a rate of 1000 samples/s. The source of each sample clock is left to the default value, which is just the internal analog input sample clock that will be derived from dividing down one of the internal timebases on the device.
Next, the reference clock source of each device is set to PXI_CLK10, which is the same principle as in the PCI reference clock above. The only difference is the fact that each PXI module synchronizes its internal timebases to the PXI backplane 10 MHz clock.
As with the PCI reference clock example, the Get Terminal Name with Device Prefix VI is used to programmatically extract the Start Trigger signal of the master device and route it to be used to start the slave device. This step is the second phase of the synchronization – making sure that they start at the same time.
The task from the slave is started first, but has to wait to receive a trigger signal from the master Start Trigger that was routed in the previous step. When the master is started, the Start Trigger signal is generated to trigger the slaves. The sequence structure is used to ensure that the slave is started before the master and to avoid race conditions.
At this step, the samples are read by both tasks. Each task will provide 1000 samples and display them on a waveform graph.
After the acquisition is done, the tasks are cleaned in this step. This step ensures that the resource is freed and can be used by another task.
This last step handles the errors that might have occurred during the acquisitions. Error clusters from both tasks are merged into one error cluster and wired into the error handler.
Example code from the Example Code Exchange in the NI Community is licensed with the MIT license.