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Part of the M Series Synchronization with LabVIEW and NI-DAQmx Example Set
The RTSI bus offers the ability to share signals between independent devices in the system. Traditionally, synchronizing data acquisition devices required sharing a common timebase clock source among the devices. M Series devices have an internal timebase of 80 MHz, which is too high a frequency to pass accurately to other devices through the RTSI bus. Typically, 10 MHz is a more stable clock frequency to route between devices and is used as a standard for synchronization in PXI systems with the 10 MHz PXI clock built into the backplane of the chassis. Therefore, M Series devices generate a 10 MHz reference clock to be used for synchronization purposes by dividing down their 80 MHz onboard oscillator. To synchronize acquisitions or generations across several PCI M Series boards, one board acts as the master and exports its 10 MHz reference clock to all of the other slave boards. The NI-STC 2 ASIC on each M Series has PLL circuitry that compares an external reference clock to its built in voltage-controlled crystal oscillator clock (VCXO) to output a clock that is synchronized to this reference. Thus each device in the system can input a 10 MHz reference clock and synchronize its own 80 MHz and 20 MHz timebases to it. With this technology, all devices are synchronized to the same 10 MHz master clock, but can use their individual faster 80 and 20 MHz timebases generated onboard. Note that due to the way signals are divided down, the 100 kHz timebase will not be in phase with the input to the PLL. Refer to Figure 1 for an overview of the timebase routing for M Series devices. Figure 1 shows how the PLL and a reference clock are used to synchronize two high-speed clocks, 100 MHz in this case.
Figure 1 Concept of Synchronization Using a Reference Clock
When routing its 10 MHz reference clock out for other devices to synchronize to, the master device can set the source of its reference clock to "OnboardClock". This option will take the 10 MHz reference clock of the master device, which has been routed out to RTSI, back to the source of its own PLL. The master device then sees the same delays that the slave devices phase locking to the 10 MHz reference clock over RTSI will see. Note that by default, the source of an M Series reference clock is set to "none". This will cause the M Series device to use its onboard oscillator as the source of its timebases.
Figure 2 shows an example of multidevice synchronization of two M Series boards using the reference clock of the master device. The labels on the figure correspond to important parts of the program and a description for each is given below.
Figure 2 PCI Synchronization with 10 MHz Reference Clock
Example code from the Example Code Exchange in the NI Community is licensed with the MIT license.