Example Code

Compensate for Different Group Delays with C Series Modules in LabVIEW FPGA

Code and Documents

Attachment

Overview

This example shows how you can compensate for different group delays with C series modules in LabVIEW FPGA on NI cRIO plattform.

Description

Group delay is a trait inherent to delta sigma converters. All of the NI C Series modules which use a delta sigma converter have a specification for group delay in the

User Manual. Group delays are typically different for each ADC and can vary depending on the sampling rates.  A method to compensate for these differences in group

delays is to use a simple feedback node which delays a signal by a fractional number of samples.

feddback node.JPG

In this example a Digital Output create a pulse. A Digital Input, a Analog Input with SAR ADC and a Analog Input with Delta-Sigma ADC measure the pulse.

NI 9401 DO 0  -->  NI 9401 DI 4

                      |

                      --> NI 9215 AI 0

                      |

                      --> NI 9229 AI 0

In the chart you can see that the feedback node delays the signals of the channels without a Sigma-Delta ADCs and the signals in the graph are now synchronous.

Chart.png

Steps to Implement or Execute Code


  1. Open the attached project, add your cRIO device and push the VIs to your cRIO. To run this example you need the C series modules NI 9401, NI 9215 and NI 9229. Details to the wiring you find in the example.
  2. Compile the FPGA VI for your target and run the Main (RT).vi.
  3. In the graph all three signals should have a rising and fallinge edge at the same time.

Please check also out the Input Delay Calculator (NI 9229).vi on My Computer in projecct.

Requirements


Software

  • LabVIEW 2016 + RT + FPGA later
  • NI-RIO 16.0 or later

Hardware

  • cRIO-90xx
  • NI 9401, NI 9215 and NI 9229




Example code from the Example Code Exchange in the NI Community is licensed with the MIT license.

Comments
mcduff
Trusted Enthusiast
Trusted Enthusiast
on

Can you downconvert to 2015? Thanks

mcduff

Wolfgang_Z.
NI Employee (retired)
on

I have attached the a 2015 version.

mcduff
Trusted Enthusiast
Trusted Enthusiast
on

Thanks!!

mcduff
Trusted Enthusiast
Trusted Enthusiast
on

Thanks for your help. I came to a similar solution, ie, using the feedback node and a counter. I had to sync a SAR with 3 sigma-deltas that were running at a different sampling rate. For the SAR I initially wanted it to run at 1MSa/s, while the sigma-delta modules were running at 51.2kSa/s. Eventually, I got the sigma-delta modules running at 50kSa/s and the SAR at 800kSa/s. By running the SAR at 800kSa/s I was able to use the master clock of the sigma-delta modules(12.8MHz) to trigger acquisition on the SAR module. There was too much drift between the FPGA clock and the sigma-delta master clock.

Thanks again.

Cheers,

Andrew

Contributors