Example Code

1-D median filter using LabVIEW FPGA

Products and Environment

This section reflects the products and operating system used to create the example.

To download NI software, including the products shown below, visit ni.com/downloads.


  • CompactRIO|SingleBoardRIO


  • LabVIEW FPGA Module
  • LabVIEW


  • NI RIO

Code and Documents



This example demonstrates how to implement a 1-D median filter in LabVIEW FPGA.


Median filter is a common non-linear filter for signal processing. It is often used to eliminate the noise in images or other signals, especially the speckle noise or salt and pepper noise. The median filter will smooth the signal while reducing the noise. The median filter runs throught the signal point by point, replacing each point with the median of the neighbouring points. Since it is a non-linear filter, we can't simply exchange a median filter with the downstream processing step, thus, we have to do it on the FPGA target to save the calculation on host PC. This example shows a prototype of 1-D median filter on FPGA.

The filter will filter the signal point by point using an 11 point window. You can expand this window by modifying the VI (see VI comments). You can use the "Host test.vi"  to compare the performance of the median filter implemented on the FPGA with the results from the "Median Filter" VI from the Signal Processing palette.




  • LabVIEW Full Development System 2012 (or compatible)
  • LabVIEW FPGA Module 2012 (or compatible)
  • LabVIEW Real-Time Module 2012 (or compatible), if you use a RealTime Target for the Host VI


  • No hardware is necessary to use this example VI. You can migrate this example to any LabVIEW FPGA Target if you want to use real hardware. You must recompile the FPGA VI if you use hardware.


Steps to Implement or Execute Code

  1. Download and open the attached ZIP-file
  2. Open the project.
  3. Host - Simulation (no hardware).vi executes the code on the local PC and doesn't need any hardware. Host - Test (with hardware).vi executes the code on a real FPGA target.


Additional Information or References

Host - Simulation (no hardware) - Front Panel.png


Host - Simulation (no hardware) - Block Diagram.png


**The code for this example has been edited to meet the new Community Example Style Guidelines. The edited copy is marked with the text ‘NIVerified’. Read here for more information about the new Example Guidelines and Community Platform.**


If you have any problem to run this example or want to create a reconfigurable median filter, please contact the author: Lei Song, National Instruments, *Lei.song@ni.com.

Example code from the Example Code Exchange in the NI Community is licensed with the MIT license.


This is very useful filter. I use it in my application to reject outliers. Works great.

The only issue is that it is difficult to extend this code.

I would love to see a document with this filter that explain what exactly need to be changed when you want to extend (change size) the filter.

I would also love to see this filter in the FPGA tools.

Thanks for the code Lei

Amit Shachaf

Amit Shachaf