Dynamic Signal Acquisition

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Bad ClockOut behavior in FlexRIO 7962R / 6585 adapter card

Hi everybody,


I am having some tricky problems when trying to set up correctly the clock out provided by the 7962R FlexRIO FPGA module along with a 6585 front end adapter card.


In fact, when sending a 150 MHz clock through DDCA Clock Out I have to switch the 'clock_out_en' signal from zero to one. At this point, I would expect to observe something similar to the attached file 'clock_flex_ok.jpg' : the clock wakes up from zero to a valid clock.


Instead, I get the plots in 'clock_flex_not_ok__20ns_div.jpg' and 'clock_flex_not_ok__50ns_div.jpg'. I don't understand why I get a modulated, increasing amplitude version of the clock I would expect. In addition, when setting 'clock_out_en' to zero I obtain a three stated output ... I am using a differential, active probe and a differential termination of 100 Ohms. 


Any idea ?


Cayetano Santos


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Message 1 of 3

This looks like the 6585 output buffer power supply is still ramping up when you assert 'clk_out_en'.


Are you setting 'clk_out_en' immediately after downloading or resetting the FPGA VI?


You could test this by adding a delay between when the FPGA VI is downloaded or reset and when you assert 'clk_out_en'.


The FlexRIO includes several 'IO Module Status' signals on the host and on the FPGA.  We recommend that you use 'IO Module IO Enabled' to determine when the IO module is ready.


To aid further debug - can you share a screenshot of your FPGA VI and which 6585 CLIP you are using?




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Message 2 of 3

I apologize for resurecting an old post but ran into the same issue.

To add to RB's solution, FPGA I/O Node--> Add new FPGA I/O--> IO Module Status--> IO Module IO Enabled.




Mohit Kapur

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Message 3 of 3