Clip Node and UCF Constrain File Error

[Jabba]

I'm using Lv FPGA 8.6.1 to call a VHDL code inside a cRIO 9103.

To do this, I'm using a CLIP node. Everything is fine with this. The VHDL code is doing exactly what I want on the target.

I just want to add some timing constrains to the output "out_port"' of the CLIP node. (See the UCF in the zip attachment).

When I try to compile the VI "Bug.vi", I get the following error:

ERROR:NgdBuild:756 - "toplevel_gen.ucf" Line 2: Could not find net(s)

   '*window/theCLIPs/MyCLIP_CLIP0/out_port*' in the design.  To suppress this

   error specify the correct net name or remove the constraint.

ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.

ERROR:NgdBuild:19 - Errors found while parsing constraint file

   "toplevel_gen.ucf". "

As the XML file is declared correctly, and the entity as an output called exactly "out_port", I don't understand why I have this error. It seems that the net path is not correct.

I think that my UCF file is correct. Is there a tricky thing I missed ? As I've tried everything, I do not have any idea.

Thanks for your help. 

[RyanB]

It is common for the Xilinx tools to rename a net during the compilation process.  This causes the port called "output_port" to no longer exist when the tools attempt to apply this constraint.  I believe you can add a 'keep' directive in your HDL code to preserve a net name and allow your constraint to work.  Review the Xilinx constraint guide for details.

However - what aspects of your CLIP interface require timing constraints?  Can you access the I/O synchronously and therefore depend on the clock period constraint to verify timing instead of the net constraint?

-RB