Measuring capacitance with PXIe-4142 SMU

[Realistic · Accepted solution]

So i went and checked the NI DCPower Measure Step Response.vi. sample. Turns out it is a better was to do the mesurment. I measured a 1uF X2 foil capacitor. The measurment is within 1nF of the LC meter measurment, so it works great. In case anyone else needs the same thing i'm providing the VI. Thank you for all your help.

[Brandon_G.]

Just curious, were you able to observe the non-linearities on the X7R with the new VI you created?  Wondering how bad they are or if there may have been something else going on with the previous implementation of the VI.

[Realistic]

Yes, there were still non-linearities on the X7R. They are bad enough to be noticeable on the graph. Also its capacitance slightly changes with the measure voltage.

[Henrik_Volkers]

---

@Realistic wrote:

Yes, there were still non-linearities on the X7R. They are bad enough to be noticeable on the graph. Also its capacitance slightly changes with the measure voltage.

---

🙂

Some actual data would be nice. There are lies, damn lies, and AD-datasheets .... don't know where the cap datasheets position 😉   Do you have a datasheet for your X7R?  Some already declaire voltage deratings...

So keep in mind: (Arbitary) Assumptions (like should not be, I assume) are AssYouMe 😄 😄

(Shameless hint: Another way to say thank you for a helping message is the KUDOS-button in lower left corner 😉 )

[Realistic]

Unfortunately i do not have a datasheet as i got the capacitor from an unmarked capacitor kit. The strange thing is however that capacitance goes up with the voltage. The capacitor is 1812 in size. 1uF.

Notice the slight nonlinearity in voltage and diviation in current.

Cheers

[Brandon_G.]

The deviation in current is due to being in voltage mode and relying on compliance to drive the output to a (mostly) constant current.  However, this is not the same thing as forcing the output to a constant current in current mode.  The reason for this is that there is a voltage control loop and a current control loop and when you are in compliance the SMU is trying to arbitrate who has control of the loop.  On the other hand, when in current mode (and not near compliance) the current loop has full control of the loop and sets the output to a steady constant current.  I would recommend changing the output to current mode.  You will have to add the Configure Output Function VI to set to current mode as the driver defaults to voltage mode.  You will also have to replace the Level Range, Limit Range and Limit VIs to their current output counterpart.  

It looks like your linearization is across the whole span of voltage but you might (hopefully?) find a more gradual local slope around 0 and a more steeper local slope near the ends. Maybe this could be the issue, but it's hard to tell with a line that's almost straight.  You can subtract the best fit line from the voltage v.s. time line to get a better visual on the non-linearities.  Also, your excitation method is different than how these caps are typically spec'd which uses a small AC signal superimposed on top of a DC signal.  This might not be the issue but it's something to consider when trying to reconcile the measurements with the spec.

[Realistic]

I have considered switching to constant current output, however if i do so it becomes impossible to do a controlled amplitude AC signal on top of a DC signal, as you can only set 1 voltage limit. Also the current diviation is not that bad, its way under 1% and its accounted for in the capacitance calculation. Plus the whole approach with setting 2 voltage points and measuring multiple points in between automatically would be out.

If you look at the first example i provided i had a constant current approach in the beginning and it didn't work. So i conclusion i am happy with the result now and don't think i could do much better even with a high amount of additional time invested.

I have upgraded the VI to use an AC signal on top of a DC signal. I got the AC signal by setting repeat on output. It does become quite difficult to determine when the signal has stabilised when doing so however. As I see no way to set the current limit higher at first (to reach DC offset) without switching to advanced sequence the measurement now takes quite a while (with higher DC offsets). I might try to solve this problem in the future if the need arieses, but right now i don't have time.

[memoryleak]

Should you or anyone else reading this decide to return to measurement improvements, might I suggest a slightly different formula:   Q=CV,  where V is a (smallish) voltage step and Q is the integral of the current sourced into the capacitance.  

The integrating ADCs on the 414x and 4135-4139 SMUs should shine here.  Successive voltage steps may be concatenated to graph C vs V, without the need for a precise slope or worrying about startup/ending conditions as both occur when no current is flowing.

Id suggest the same Measure Step Response VI as an excellent starting point 🙂