We are considering using the NI sbRIO-9627 to provide a stable and low jitter clock signal (20MHz clock derived from the 40MHz internal oscillator fed to the FPGA) for sigma-delta ADC’s. This would be achieved using the sbRIO CLIP generator in order to connect some DIO pins to the FPGA clock lines and feeding them to the clock input pins of the ADC. We would like to get an estimate of the amount of clock jitter that we would expect to observe.
Additionally, page 73 of the
7 series FPGA clocking resources guide mentions that “MMCMs and PLLs reduce the jitter inherent on a reference clock.
The MMCM and PLL can be instantiated as a standalone function to support filtering jitter from an external clock before it is driven into another block”. Would this jitter filtering functionality be automatically implemented when using the sbRIO CLIP generator to derive the 20MHz clock from the 40MHz clock or would it require manually writing/editing VHDL code to implement it? ( I understand that we can reserve MMCM resources when using the CLIP generator but is it possible to access these resources from LabVIEW FPGA?)
