iodelay example ni6587

[Jeff_Giacone]

I am looking for an example that utilized the iodelay feature of the xilinx Vertex 5.

I'm trying to develop an auto-delay feature to adust the input data relative a source sync clock hence to place the data in the optimum timming location for data capture

[Jesse_D]

Hi Istutiger, 

You can't use primitives in LabVIEW FPGA. The compiler will take care of writing the lower level code for you. It sounds like the function you need is the Discrete Delay Function, there are examples at the bottom of the page. It also has a dynamic option that might work very well for what you are doing.

You may find the FPGA help and some of our Tutorials helpful. 

[Jeff_Giacone]

I am looking for sub-clock skew adjust

[Jesse_D]

Hi Isutiger, 

Can you give more information about what you are trying to do? Are you using FlexRIO or cRIO? 

If you need to implement VHDL you can use the IP Block to run custom code. 

[Jeff_Giacone]

Hi,

[Jeff_Giacone]

Jessie,

I am trying to integrate Xilinx xapp860 and Flexrio with Adapter module NI 6587, FiniteAcqExtClkStartTrig

I want to automatically deskew a couple of Acqusistion serial data channels with a Strobe clock  

[Jeff_Giacone]

Is there an example on how to integrate VHDL code and a custom IP?

[Jesse_D]

Hi Isutiger, 

There is a good tutorial here and example here, and a good overview here.

[Jesse_D]

Hi Isutiger, 

There also may be an option for using the CLIP for the 6587. Looking at the help for the flexRIO (which can be downloaded here), there is an IDELAY function for the Serdes CLIP or Serdes Connector CLIP that is implemented already.

The diagram for this delay is shown below:

From the help: 

Acquisition channels are connected to IDELAY blocks, which allow for per channel data delay. Each Chx_Idelay_Increment andPFIx_Idelay_Increment signal corresponds to its respective channel. A logic high level increases the data delay by one tap perAcq_Regional_Clock cycle or PFI_Regional_Clock cycle. In this CLIP, a tap is equal, nominally, to 78.125 picoseconds when the IDelay_Calibration_Clock signal is set to 200 MHz. For more information about IDELAY and taps, refer to Chapter 7: SelectIO Logic Resources in the Virtex-5 FPGA User Guide available at www.xilinx.com.

This may be a much easier way of implementing your delay. Do you have a Serdes CLIP? 

[Jeff_Giacone]

Jessie,

Thanks for the information.

I did see that information in the user manual, and it's part of the SERDES clip, I was just looking for an easy way to auto tune the I/O delay.

My UUT has a PRBS output which could be used as the source signal for the Flexrio data capture interface